應用於骨導式人工耳蝸之低功耗聲音訊號處理器設計與實作

Abstract

人工耳蝸是一種植入式的電子裝置，可使重度聽障患者恢復部分聽覺。不同於助聽器，人工耳蝸不是只將聲音放大，而是藉由電流脈衝直接對耳蝸內未受損的聽神經加以刺激以產生聽覺。本論文提出一個可用於新式骨導式人工耳蝸的低功耗聲音訊號處理器，完成演算法開發、硬體架構、以及晶片實現。此處理器包括適應性波束形成器、實數運算的快速傅立葉轉換、包絡檢測、通道組合、以及對數函數壓縮。在晶片實現上，藉由實數傅立葉轉換的演算法、暫存器個數最小化、及資料分配最佳化、數位座標旋轉運算器、以及最低耗能點操作等技巧，達到低功耗與減少面積的設計。相較於複數傅立葉轉換，實數傅立葉轉換可節省44.36%的功率消耗，暫存器個數最少化及資料分配最佳化的應用，使傅立葉轉換的輸出調序電路在面積上減少28.07%，功率消耗降低27.09%。此外，在包絡檢測與對數函數壓縮這兩個較複雜的運算中，藉由數位座標旋轉運算器達到電路延遲時間和功率的優化。此晶片以90 nm CMOS製程實現，核心面積為0.47 mm^2。操作在50 kHz以及最低耗能之0.34 V核心電壓，晶片達到最低耗能，每次運算消耗14 nJ，其功率消耗與訊號處理延遲分別為4.8 uW和2.94 ms。

A cochlear prosthesis is an implanted electronic device that can restore partial hearing of profoundly deaf people. Unlike a hearing aid, which is for acoustic signal amplification, a cochlear prosthesis stimulates undamaged auditory nerves of patients through electric currents. This thesis presents the acoustic signal processing, hardware architecture, and chip implementation of a low-power acoustic signal processor for a bone-guided cochlear prosthesis. The developed processor contains blocks for adaptive beamforming, real-valued FFT, envelope detection, channel combination, and log-compression. Power- and area- efficient design is achieved by leveraging several techniques, such as dedicated real-valued FFT, register count minimization, data allocation optimization, hardware complexity reduction, and minimum-energy-point operation. Compared to the complex-valued FFT, real-valued FFT achieves 44.36$\%$ power reduction. For FFT output reordering, register count minimization and data allocation are applied, yielding 28.07% and 27.09% area and power reduction, respectively. Envelope detection and log-compression are realized by hardware-efficient CORDIC engines. The proposed acoustic signal processor chip is designed and fabricated in a 90 nm CMOS process and the core area is 0.47 mm^2. The energy dissipation of the chip is minimized to 14 nJ per operation by operating at 50 kHz drawing from 0.34 V. The power dissipation and latency are 4.8 uW and 2.94 ms, respectively.