漸進式光子映射之高效率漸進式光輝估計引擎設計與實作

Abstract

在本論文中，我們提出了一個漸進式光輝估計引擎硬體架構來加速漸進式光子映射的計算。此架構中包含了四個漸進式光輝估計單元、光通量修正控制器以及光輝估計控制器。漸進式光輝估計單元可以透過硬體共用運算光通量修正和光輝估計以及採用管線架構來加速光輝估計的運算，透過光通量修正控制器和光輝估計控制器可以使得資料更有效率的給四個漸進式光輝估計單元平行運算以及預防資料相依性造成的錯誤。此設計已使用TSMC 90奈米製程實現面積為1.78 mm2，根據晶片模擬顯示，我們所提出的架構在頻率125 MHz下可達到496 MHpO/s及功率消耗為184 mW。

In this work, a progressive radiance estimation engine (PREE) hardware architecture is proposed to accelerate the processing of the progressive photon mapping. The proposed PREE architecture consists of four progressive radiance estimation units (PREUs), flux correction controller (FCC) and radiance evaluation controller (REC). PREU can share hardware resource for flux correction and radiance evaluation and adopts pipeline to accelerate the radiance estimation computation. Through FCC and REC, the data can be efficiently dispatched to gain the better parallel computing and prevent data dependency with four PREUs, respectively. The proposed PREE architecture is implemented in TSMC 90 nm CMOS process with the core area of 1.78 mm2. According to the post-layout simulation results, the proposed PREE architecture implementation can achieve the hit-point rate of 496 MHpO/s and consumes the power by 184 mW at 125 MHz.