以基於良率的電源接墊增置方法強化晶片上的電源供應網路

Abstract

本篇論文提出一個藉由加入額外凸塊以強化電源供應網路的方法。在增置凸塊的同時，我們也將封裝凸塊的良率納入考量。在獲悉封裝凸塊的良率之後，我們使用一個簡單有效的方法估算出連接至電源網路的晶片元件的良率，然後再決定需要增置凸塊的位置。在增置凸塊的過程中，找出封裝良率較高的接墊位置是很重要的，良率佳的接墊位置不只能讓凸塊更容易達成良好的電性連接也能使增置的凸塊不易損毀而能有效提升晶片與元件的良率。我們使用蒙地卡羅演算法來驗證我們的實驗結果並與前人的相關研究做比較。實驗結果顯示，當使用者採用符合現代封裝趨勢的良率模組來設計電源供應網路，比起前人的作法，我們提出的方法能夠使用更少的凸塊來達到更好的晶片良率。此外，即使是採用尚未成熟而良率不甚理想的封裝製程來做設計，我們提出的演算法依然能將晶片良率改善到95%以上。這份研究明確地指出，要設計一個強韌的電源供應網路就必須將封裝良率的影響加入考量。

In this paper, we propose a method to enhance on-chip power supply network robustness by adding additional power pads based on package yield model. We use a simple method to analyze the yield of devices connected to power network and decide which locations can be added with redundant power pads. During pad assignment process, choosing a candidate location with higher probability to make a successful contact bump can improve both device and chip yield. We use Monte-Carlo simulation to verify our experimental result and compare the result with the previous work. The experimental results show that our proposed method can use less redundant power pads to enhance the chip yield to a better situation when a modern package yield model is applied. Furthermore, when a low yield package model is applied, our algorithm also has the ability to improve the chip yield to more than 95%. This shows the importance of taking package yield model into consideration to design a robust power network.