本質參數擾動對於低操作電壓塊材鰭式場效應電晶體元件特性與電路功率消耗變異之研究

Abstract

鰭式場效應電晶體是次16奈米技術節點最具發展性的立體結構之一。為了降低本質參數中的隨機摻雜擾動，相對於重通道摻雜(摻雜濃度大於1.5x1018 cm-3)的元件而言，低通道摻雜(摻雜濃度在1017 cm-3左右或以下)的元件提供新的技術方向。另一方面為了降低低消耗功率(LP；臨界電壓偏高約260 mV)與快速操作(HS；臨界電壓偏低約140 mV)元件的功率消耗，降低外加電壓(VDD由0.6 降到0.8 V)亦為下世代的元件趨勢。研究元件操作在不同的臨界電壓與外加電壓時的特性擾動成為迫切的議題之一。對於次16奈米LP及HS的高介電金屬閘塊材鰭式場效應電晶體與電路在VDD = 0.6 以及0.8 V，本論文採用實驗校估過的三維度元件暨電路整合模擬技術來探討上述元件技術在遭受本質參數擾動時的特性變異，其中本質參數擾動源包含了：通道隨機摻雜擾動(RDF)、隨機金屬閘極功函數擾動(WKF)、通道與絕緣層介面缺陷擾動(ITF)。除了元件的直流、交流特性外，本研究討論數位電路在靜態與動態操作時直流轉換特性曲線、雜訊邊限、相關時序參數、以及功率消耗遭受本質參數擾動時的特性變異。 經由大樣本的統計元件暨電路模擬結果我們得知：在直流的情況下，與同時考慮每個擾動源項(ALL；同時考慮RDF、WKF以及ITF) 的情況相比，由各個單一項所造成臨界電壓擾動而取出的統計和(SUM = (Vth,RDs + Vth,WKs + Vth,ITs)0.5)會有高估的情況。關於閘極電容的部分汲極採用低電壓(VD = 0.05 V)，相對於直流的高汲極電壓(VD = VDD)而言，靠近汲極端的擾動受汲極電壓壓抑的情形較不明顯，所以，SUM的最大閘極電容擾動相對於ALL則會有低估的現象發生。除此之外，快速操作元件在不同VDD時，不論直流的本質參數或最大閘極電容擾動皆會因為通道隨機摻雜擾動的消失而獲得良好的改善。 對於上述低消耗功率及快速操作元件在不同外加偏壓所構成不同的元件技術的反相器電路而言，因為雜訊邊限(NM)與元件的臨界電壓有關，故雜訊邊限擾動與元件的臨界電壓擾動趨勢相同，也就是：ALL > RDF > WKF > ITF。對時序參數而言，下降時間 (tf；輸出電壓(Vout)從90%至10%的時間差)與上升時間 (tr； Vout從10%至90%的時間差)對應到n型與p型元件的放電與充電能力，且在低消耗功率及快速操作元件在外加偏壓VDD為 0.6 V時，各項次(ALL、RDF、WKF以及ITF)的tf、tr與平均延遲時間的趨勢則跟NM相同。然而，在低消耗功率及快速操作元件在外加偏壓VDD 為0.8 V時，因為各個擾動源造成的擾動在Vout為90%時十分接近，所以，tr擾動的大小依次為: ALL > ITF > WKF > RDF。因為低消耗功率元件在外加偏壓VDD 為0.6 V時的充放電能力嚴重不足，所以其時間參數的擾動會大於5%。對於反相器電路的功率消耗方面計有：靜態功率 、動態功率 、與短路功率 ，由公式可知，上述反相器電路的功率消耗主要是由VDD所主導。由於靜態功率中的漏電流與臨界電壓呈指數關係遞減，因此漏電流隨著臨界偏壓的上升，其漏電流會急遽下降，進而使得對於相同外加偏壓VDD下低消耗功率及快速操作元件所組成的電路的靜態功率比值隨漏電流的比值改變。值得一提的是，在上述不同元件技術下所組成的反相器電路中，除了規一化(Normalized)靜態功率的擾動較為顯著外，其餘兩項功率的擾動在5%以下。對於低消耗功率及快速操作元件在相同外加偏壓VDD之功率消耗，快速操作元件的技術所組成的反相器電路會因為通道隨機摻雜擾動的消失而擾動得以獲得改善。 總之，本論文已研究次16奈米低消耗功率與快速操作的高介電金屬閘塊材鰭式場效應電晶體與電路在0.6與0.8伏特的外加偏壓下，本質參數擾動對於各種特性變異的影響，此新的研究成果足以提供我國半導體產業相關製程與元件技術發展之參考。

Nowadays, FinFET is one of the most promising vertical channel structures while the technology node extends to 16 nm. Comparing with the low power (LP; threshold voltage (Vth) equals to 260 mV) devices that the channel doping is not smaller than 1.5x1018 cm-3 called the heavily doped channel, the lightly doped channel which is not larger than 1017 cm-3 for the high speed (HS; Vth equals to 140 mV) devices provide a new technique evaluation to reduce the intrinsic fluctuation. To narrow the power consumption on the LP and HS devices, scaling down the applied voltage (VDD; from 0.6 V to 0.8 V) is the trend of the next-generation. Therefore, for the devices with different Vth and VDD, the fluctuation of devices characteristics has been one of the urgent issues to study. For the sub-16 nm LP and HS high-k/metal gate (HKMG) bulk FinFET devices with VDD equaling to 0.6 V and 0.8 V, in this thesis, we use 3D experimentally calibrated device and circuit simulation to investigate the intrinsic fluctuations of studied devices including the random dopant fluctuation (RDF), random workfunction fluctuation (WKF), and interface trap fluctuation (ITF). We focus on not only the device's DC/AC characteristics, but also the characteristics in digital circuit, such as the power consumption, DC transfer properties, associated timing parameters, and noise margin (NM). From simulation results of statistically numerous samples, under the DC bias, statistical sum of Vth with respect to each associated fluctuation sources (SUM = (Vth,RDs+Vth,WKs+Vth,ITs)0.5) has been overestimated compared with the devices' fluctuation suffering from fluctuation sources simultaneously (ALL; consider RDF, WKF, and ITF concurrently). Since the drain bias of DC (VD = VDD) is larger than that of AC (VD = 0.05 V), near the drain side, the fluctuated potential is more significant in AC condition. As a result, SUM of maximum gate capacitance (Cg, max) has been underestimated compared with ALL of it. Besides, for the HS devices, both of the intrinsic parameters in DC and Cg, max in AC would be improved due to the elimination of RDF. As for the inverter circuits composed of aforementioned LP and HS devices with different VDD, due to association between NM and device's Vth, the trend of fluctuations of NM is the same as that of the Vth for the device in DC condition: ALL > RDF > WKF > ITF. Falling time (tf; the time required for the output voltage (Vout) to fall from 90% of thelogic“1” level to 10% of the logic “1” level.)/raising time (tr; the time required for the Vout to rise from 10% of thelogic“1” level to 90% of the logic “1” level.) is corresponding to the capability of discharging/charging of n-/p-type devices for the timing parameters of aforesaid inverter circuits. Also, the fluctuation trend of tf, tr, and average propagation delay time is the same as the NM's. However, while VDD equals to 0.8 V, the fluctuation of each term (i.e., ALL, RDF, WKF, and ITF) for the Vout at 90% of the logic “1” level is almost the same. As a consequence, the fluctuation of tr is: ALL > ITF > WKF > RDF in sequence. The fluctuations of timing parameters are larger than 5 % because of the poor capability of charging and discharging due to the low VDD equaling to 0.6 V and high Vth. The relative equations about power consumption in inverter circuit: (static power consumption) , (dynamic power consumption) , and (short circuit power consumption) imply that power consumption is governed by VDD. Since the relationship between leakage current and Vth is exponential decay, the increasing Vth results in dramatically reducing leakage current, where the change of ratio on static power consumption of LP as well as HS circuits with same VDD follows the change of ratio on leakage current of that. Notably, for the before-mentioned inverter circuits, in addition to the severe fluctuation for the normalized standard variation of static power consumption, other power consumption terms have been suppressed below 5%. Owing to the elimination of RDF, the power consumption in the HS inverter circuit has been lightly improved compared with that in the LP inverter circuit. In this thesis, we have successfully investigated the impact of intrinsic parameters fluctuation on characteristic variability of sub-16-nm LP as well as HS HKMG bulk FinFET device and circuit with VDD = 0.6 and 0.8 V. The main findings of this research are useful for developing advanced fabrication and device technologies in semiconductor industry.