適用於三角積分式類比數位轉換器之全整合型內建自我測試電路設計

Abstract

隨著製程微縮技術越發困難，半導體產業界相信 3D IC 將會是未來IC 設計重要趨勢，像是through-silicon via (TSV)這類的3D IC 技術可提供電路間短距離的垂直連接，使電路效能再創新高。然而，IC 測試技術在3D IC 面臨許多前所未見的挑戰，其中最大的瓶頸在於3D IC 的I/O 腳位可能只存在於最上層或最下層晶片，內層晶片缺乏與外部直接連接的I/O 腳位，因此傳統的測試技術可能無法直接應用在3D IC 上。專家學者紛紛對3D IC 提出了測試策略，一致認同可測試性設技(design-for-testability, DFT)及內建自我測試(built-in self-test, BIST)將是測試3D IC 不可或缺的兩項關鍵技術。 本論文提出了兩個適用於三角積分式類比數位轉換器之全整合型(fully integrated)內建自我測試電路設計，可準確測試三角積分式類比數位轉換器之訊號雜訊失真比、動態範圍、頻率響應、增益誤差、偏移量等參數。待測三角積分式類比數位轉換器之輸入級使用了去耦合可數位測試性設計(de-correlating design-for-digital-testability)，此設計藉由重新規畫(reconfigure)原有輸入級類比電路，可接受經脈波密度調變之數位位元串流訊號並將之轉換為測試所需之高精準度類比訊號，大幅降低類比測試訊號產生器之設計複雜度。本論文所提出之第一個內建自我測試電路設計使用了modified controlled sine wave fitting 演算法，在時域上對類比數位轉換器之輸出響應進行即時分析運算，故不需龐大的記憶體儲存所分析之輸出樣本，亦不需成本高昂的CPU 或DSP，電路實現上只使用了9.9 k 個數位邏輯閘。此全整合型內建自我測試三角積分式類比數位轉換器晶片是以0.18-um CMOS 製程設計製造，此晶片更進一步與HOY 無線測試平台整合進行測試，成功驗證了對類比及混合訊號電路進行無線測試的可行性。此內建自我測試電路可達到16 kHz 的可測試輸入頻寬，相當接近待測類比數位轉換器之20 kHz 輸入頻寬。 前一內建自我測試電路的測試準確度與彈性已遠高於已知文獻的結果，但其受限的可測試輸入頻寬仍稍嫌遺憾，因此我們進一步提出了in-phase and quadrature waves fitting演算法，不僅保有即時運算、低硬體成本的特性，更可解決先前可測試輸入頻寬受限的問題。此全整合型內建自我測試三角積分式類比數位轉換器同樣以0.18-um CMOS 製程設計製造，晶片量測結果顯示此內建自我測試電路成功達到了20 kHz 之全頻寬測試。 本論文實現了兩個全整合型內建自我測試之三角積分式類比數位轉換器設計，可準確測試三角積分式類比數位轉換器之重要效能參數，且不需使用傳統測試高解析度類比數位轉換器必備的高階類比及混合訊號測試機台，大幅降低測試成本，成功達成了低成本與高測試準確度的設計目標，更提供3D IC 一個完善的類比數位轉換器測試解決方案。

3D ICs are considered as one of the emerging techniques for implementing the next-generation ICs. 3D IC techniques such as through-silicon via (TSV) provide vertical and shorter connections for inter-die communication. Thus, the 3D IC achieves many advantages such as decreased power, reduced signal latency and higher performance. However, the 3D structure leads to new test challenges. The main issues of testing 3D ICs are the reduced controllability and observability due to the lack of accessible I/O pads. From this point of view, the circuits under test incorporated with some on-chip design-for-testability (DFT) or built-in self-test (BIST) functions are highly demanded for 3D ICs. In this dissertation, we propose two fully integrated BIST designs to test the signal-to-noise-and-distortion ratio (SNDR), dynamic range, frequency response, gain error, and offset of Delta-Sigma ADCs. The Delta-Sigma ADC under test (AUT) adopts the de-correlating design-for-digital-testability (D3T) scheme to implement the input stage. The D3T scheme can convert a pulse-density-modulated (PDM) bit-stream into the required high-quality analog stimulus. In this way, the design effort of the high-precision analog stimulus generator is greatly eased. The first BIST design uses the modified controlled sine wave fitting (MCSWF) method. Benefiting from its real-time simple computations, the MCSWF BIST design needs neither bulk memory to store the analyzed samples nor a costly CPU/DSP. The hardware overhead of the all-digital BIST circuit design is only 9.9 gates. The fully integrated BIST Delta-Sigma ADC has been fabricated in a 0.18-um CMOS process and was tested on the HOY wireless test platform to exhibit the possibility of wirelessly testing analog and mixed-signal (AMS) circuits. Experimental results show that the MCSWF BIST design achieves a test bandwidth of 16 kHz which is very close to the rated 20-kHz bandwidth of the Delta-Sigma AUT. To address the test bandwidth limitation, we propose the in-phase and quadrature waves fitting (IQWF) method which retains the real-time computation feature. The second fully integrated BIST Delta-Sigma ADC has been fabricated in a 0.18-um CMOS process. Measurement results show that the IQWF BIST design successfully achieves a test bandwidth as wide as the rated 20-kHz bandwidth of the Delta-Sigma AUT. The proposed BIST designs eliminate the need of AMS ATE without compromising test quality, and thus greatly reduce the test cost. Most importantly, they provide test solutions for the applications in which conventional test resources are not available such as 3D ICs.