标题: | 适用于三角积分式类比数位转换器之全整合型内建自我测试电路设计 Fully Integrated BIST Circuit Designs for Delta-Sigma ADCs |
作者: | 洪绍峰 Hung, Shao-Feng 洪浩乔 Hong, Hao-Chiao 电控工程研究所 |
关键字: | 内建自我测试;三角积分式類比數位转换器;類比數位转换器测试;類比及混合讯号电路测试;3D IC 测试;Built-in self-test;Delta-Sigma Analog-to-digital converter;ADC test;Analog and mixed-signal test;3D IC test |
公开日期: | 2015 |
摘要: | 随着制程微缩技术越发困难,半导体产业界相信 3D IC 将会是未來IC 设计重要趋势,像是through-silicon via (TSV)这類的3D IC 技术可提供电路间短距離的垂直連接,使电路效能再创新高。然而,IC 测试技术在3D IC 面臨许多前所未見的挑战,其中最大的瓶颈在于3D IC 的I/O 脚位可能只存在于最上层或最下层晶片,内层晶片缺乏与外部直接連接的I/O 脚位,因此传统的测试技术可能无法直接应用在3D IC 上。专家学者纷纷对3D IC 提出了测试策略,一致认同可测试性设技(design-for-testability, DFT)及内建自我测试(built-in self-test, BIST)将是测试3D IC 不可或缺的兩项关键技术。 本論文提出了兩个适用于三角积分式類比數位转换器之全整合型(fully integrated)内建自我测试电路设计,可准确测试三角积分式類比數位转换器之讯号杂讯失真比、动态范围、频率响应、增益误差、偏移量等參數。待测三角积分式類比數位转换器之输入级使用了去耦合可數位测试性设计(de-correlating design-for-digital-testability),此设计藉由重新规画(reconfigure)原有输入级類比电路,可接受经脉波密度调变之數位位元串流讯号并将之转换为测试所需之高精准度類比讯号,大幅降低類比测试讯号产生器之设计复杂度。本論文所提出之第一个内建自我测试电路设计使用了modified controlled sine wave fitting 演算法,在时域上对類比數位转换器之输出响应进行即时分析运算,故不需庞大的记忆体储存所分析之输出样本,亦不需成本高昂的CPU 或DSP,电路实现上只使用了9.9 k 个數位邏辑闸。此全整合型内建自我测试三角积分式類比數位转换器晶片是以0.18-um CMOS 制程设计制造,此晶片更进一步与HOY 无线测试平台整合进行测试,成功验证了对類比及混合讯号电路进行无线测试的可行性。此内建自我测试电路可达到16 kHz 的可测试输入频宽,相当接近待测類比數位转换器之20 kHz 输入频宽。 前一内建自我测试电路的测试准确度与弹性已远高于已知文献的结果,但其受限的可测试输入频宽仍稍嫌遗憾,因此我们进一步提出了in-phase and quadrature waves fitting演算法,不仅保有即时运算、低硬体成本的特性,更可解决先前可测试输入频宽受限的问题。此全整合型内建自我测试三角积分式類比數位转换器同样以0.18-um CMOS 制程设计制造,晶片量测结果显示此内建自我测试电路成功达到了20 kHz 之全频宽测试。 本論文实现了兩个全整合型内建自我测试之三角积分式類比數位转换器设计,可准确测试三角积分式類比數位转换器之重要效能參數,且不需使用传统测试高解析度類比數位转换器必备的高阶類比及混合讯号测试机台,大幅降低测试成本,成功达成了低成本与高测试准确度的设计目标,更提供3D IC 一个完善的類比數位转换器测试解决方案。 3D ICs are considered as one of the emerging techniques for implementing the next-generation ICs. 3D IC techniques such as through-silicon via (TSV) provide vertical and shorter connections for inter-die communication. Thus, the 3D IC achieves many advantages such as decreased power, reduced signal latency and higher performance. However, the 3D structure leads to new test challenges. The main issues of testing 3D ICs are the reduced controllability and observability due to the lack of accessible I/O pads. From this point of view, the circuits under test incorporated with some on-chip design-for-testability (DFT) or built-in self-test (BIST) functions are highly demanded for 3D ICs. In this dissertation, we propose two fully integrated BIST designs to test the signal-to-noise-and-distortion ratio (SNDR), dynamic range, frequency response, gain error, and offset of Delta-Sigma ADCs. The Delta-Sigma ADC under test (AUT) adopts the de-correlating design-for-digital-testability (D3T) scheme to implement the input stage. The D3T scheme can convert a pulse-density-modulated (PDM) bit-stream into the required high-quality analog stimulus. In this way, the design effort of the high-precision analog stimulus generator is greatly eased. The first BIST design uses the modified controlled sine wave fitting (MCSWF) method. Benefiting from its real-time simple computations, the MCSWF BIST design needs neither bulk memory to store the analyzed samples nor a costly CPU/DSP. The hardware overhead of the all-digital BIST circuit design is only 9.9 gates. The fully integrated BIST Delta-Sigma ADC has been fabricated in a 0.18-um CMOS process and was tested on the HOY wireless test platform to exhibit the possibility of wirelessly testing analog and mixed-signal (AMS) circuits. Experimental results show that the MCSWF BIST design achieves a test bandwidth of 16 kHz which is very close to the rated 20-kHz bandwidth of the Delta-Sigma AUT. To address the test bandwidth limitation, we propose the in-phase and quadrature waves fitting (IQWF) method which retains the real-time computation feature. The second fully integrated BIST Delta-Sigma ADC has been fabricated in a 0.18-um CMOS process. Measurement results show that the IQWF BIST design successfully achieves a test bandwidth as wide as the rated 20-kHz bandwidth of the Delta-Sigma AUT. The proposed BIST designs eliminate the need of AMS ATE without compromising test quality, and thus greatly reduce the test cost. Most importantly, they provide test solutions for the applications in which conventional test resources are not available such as 3D ICs. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT079812816 http://hdl.handle.net/11536/125859 |
显示于类别: | Thesis |