三維積體電路之超薄緩衝層技術於細間距銅/錫襯墊接合開發及電性研究

Abstract

本篇論文利用超薄緩衝層技術於銅/錫接合結構中，成功開發出近次微米厚度之晶圓級細間距銅/錫襯墊接合，並探討其材料特性、接觸電阻特性、鏈接結構之電阻特性，以及可靠度的研究。其中，四種常見的半導體相容金屬材料，如:鈦、鎘、鈷和鎳皆被進行材料分析與機械強度測試，以評估其作為超薄緩衝層於銅/錫襯墊接合的可行性，研究結果顯示當選用鈷或鎳為超薄緩衝層時，晶圓級次微米銅/錫接合展現出良好的接合均勻性和強健的接合強度。 同時，16微米間距之具金屬鎳超薄緩衝層銅/錫凸塊被製備於晶圓上，藉由晶圓接合，每單位晶片中，密度高達3.4 #westeur024# 10^5/cm2之數萬個串聯銅/錫金屬內連線也被呈現於本研究中，不但具有精準的對準結果外，此結構也有穩固的機械強度抵抗研磨時所造成的應力。此外，我們在具金屬鎳超薄緩衝層之銅/錫凸塊接合上進行晶片級之克爾文測試結構及6個凸塊鏈接的電性和可靠度分析，本研究發現此結構具有良好的電性，且可以在濕度測試環境下非常穩定，更可以抵抗熱應力的測試。基於良好的機械性質、接合品質，以及電性與可靠度結果，超薄緩衝層技術於次微米銅/錫襯墊接合可被應用於未來超級整合系統中之三維垂直內連線上。

A fine-pitch submicron Cu/Sn bonding scheme has been successfully developed to realize hyper integration. By inserting an ultra-thin buffer layer, near sub-micron thickness Cu/Sn pad bonding in wafer level can be achieved. Four kinds of ultra-thin buffer layers, including Ti, Pd, Co, and Ni are evaluated, and submicron Cu/Sn bonded structure with Co or Ni ultra-thin buffer layer shows the excellent bonding uniformity and the robust bonding strength. Tens of thousands series Cu/Sn with Ni ultra-thin buffer layer interconnects in 16-μm pitch are also demonstrated with accurate alignment. The bonded pairs with a density of 3.4 #westeur024# 105/cm2 bump show the strong mechanical strength against grinding process. In addition, the modified Kelvin structure and daisy chain with series of six bonded bumps in chip level are fabricated and completely investigated on electrical characteristics. Several critical reliability assessments, such as thermal cycle test and un-bias highly accelerated stress test, are also investigated and show good stability with little degradation to withstand harsh conditions. With excellent mechanical properties, bonding quality, electrical and reliability results, the scheme of Cu/Sn pad bonding with the ultra-thin buffer layer technique is suitable for future 3D vertical interconnects.