3.1-10.6 GHz超寬頻低雜訊放大器及24 GHz低功率高增益接收機前端電路之設計與分析

Abstract

本論文討論分為兩部分，其中各部分所提出電路之晶片製作皆由TSMC 0.18μm mixed-signal/RF CMOS 1P6M製程來實現。 第一部分為應用於WPAN之超寬頻低雜訊放大器，此放大器利用了共閘極作寬頻匹配，並加上雜訊抵消之技巧，降低雜訊對輸出端的貢獻，也能有良好的寬頻匹配，此外，小訊號增益也因此提升。量測結果顯示，小訊號增益為9.7~11.6 dB，雜訊指數為4.54~4.85 dB，IP1dB為-19 dBm，IIP3為-9.5 dBm，功率損耗為16.9 mW。 第二部分則提出一個應用於24-GHz ISM band之接收機前端電路，此接收機電路包含低雜訊放大器、巴倫(平衡-不平衡轉換器)、降頻器與中頻放大器。在低雜訊放大器的設計中，使用兩級的一對共源極串疊共閘極，在一定的功率消耗下，有著良好的增益與低雜訊；在降頻器的設計中，在轉導級使用交感耦合，並搭配上電流注入的方式，使整體有高增益和低功率的表現，並在後端加入中頻放大器，使增益再提升，因此相較於其他相同頻帶的文獻，此前端電路擁有高增益低功率之優點。結果顯示其轉換增益為37.1 dB，雜訊指數為5.65 dB，IP1dB為-33.5 dBm，OP1dB為2.1 dBm、IIP3為-23 dBm，整體功率損耗為37.1 mW。

This thesis consists of two parts. All the proposed circuits were implemented in TSMC 0.18μm mixed-signal/RF CMOS 1P6M technology. Part I presents an ultra-wide band low-noise amplifier applied to WPAN (Wireless Personal Area Network.), and a common gate architecture and noise-cancelling technique are employed in this amplifier. Using these techniques can not only suppress the total noise contribution in the output but increase the total gain with an excellent input wideband matching. According to the measured results, the LNA achieves the small signal gain of 9.7~11.6 dB, a noise figure of 4.54~4.85 dB, the input P1dB of -19 dBm, and the input IP3 of -9.5 dBm over the whole working range. The power consumption is about 16.9 mW at the supply voltage of 1.8V. Part II proposes a low-power high-gain receiver front-end applied to 24-GHz ISM band. The receiver front-end contains a low-noise amplifier, a transformer balun, a down-conversion mixer and an intermediate frequency amplifier. In LNA design, using two stage common source structure cascaded with common gate structure realizes performance of high gain and low-noise with the limited power dissipation; in down-conversion mixer design, making use of cross-coupling and current-bleeding techniques obtains high gain and low power consumption. Furthermore, an intermediate frequency amplifier is added after the down-conversion mixer so the whole conversion gain increases once more. Therefore, the proposed receiver front-end has advantage of low power and high gain compared to other researches. This circuit achieves a conversion gain of 37.1 dB and a double-side band noise figure of 5.65 dB with the input P1dB of -33.5 dBm, output P1dB of 2.1 dBm, and input IP3 of -23 dBm consuming 37.1 mW.