製程變異、金屬功函數擾動及隨機摻雜擾動對 10 奈米全閘極奈米線場效應電晶體特性之研究

Abstract

當技術節點在次16奈米以下的時候，結構微縮的工作變得越來越麻煩。平面式電晶體已無法滿足多樣化資通訊晶片使用上的需求。因此，多閘極結構被提出來改善目前的情況。其中，全閘極奈米線場效應電晶體是最受人矚目的結構。此外，擾動的問題也變得益發重要。製程變異、隨機摻雜擾動和隨機功函數擾動是較主要的擾動源。在此篇論文內使用經由全量子力學理論與實驗校估過的三維度量子修正元件模擬技術來探討本質參數擾動對10奈米全閘極奈米線場效應電晶體的影響。對隨機摻雜擾動的部分，從源/汲極延伸處而來的摻雜形成不可忽略的擾動源。當通道摻雜濃度下降時，它的影響會更加巨大，所以研究上也必須把它加進來討論。研究發現臨界電壓擾動的最大值發生在多數摻雜聚集在傳導能帶圖最高點的位置，而且這個現象不受隨機摻雜擾動機制的影響

在製程變異的部分，本研究探討了閘極長度、理想圓柱形元件的半徑、非完美橢圓結構中長短軸縱橫比及氧化層厚度的變異。結果顯示出氧化層厚度的變異小到可以忽略，而理想圓柱形元件的半徑及非完美橢圓結構中長短軸縱橫比對元件的影響最大。本研究透過一個轉換公式連結這兩個元件參數。雖然擁有大縱橫比的元件有較差的短通道參數，卻有較好的製程變異抑制能力。研究隨機摻雜擾動和製程變異一起的影響，發現小縱橫比的元件有較小的擾動，因為它有較小的有效半徑，使它有更好的通道控制能力。

在隨機功函數擾動的部分，擾動主要是由高功函數金屬晶粒的數量及位置所影響。越多的高功函數金屬粒聚集在靠近源極處，元件特性將會退化地更嚴重。製造出擁有遠小於閘極面積金屬粒的閘極可有效減少擾動對元件的影響。與三閘極場效應電晶體相比之下，全閘極奈米線場效應電晶體對擾動問題擁有更佳的抑制能力。若同時考慮隨機功函數擾動及製程變異，擁有小縱橫比的元件受到更嚴重的擾動，這跟隨機摻雜擾動所表現出來的趨勢不一樣。

總之，本研究探討了幾個重要的擾動源對全閘極奈米線場效應電晶體的影響。研究成果可提供給半導體工業界去研發更先進的元件結構、材料與製程技術來提昇晶片的性能。

As the technology node extends to sub-16 nm, the task of device scaling is getting more troublesome. Planar MOSFET could not satisfy the demand of performance. Hence, new structure such as multi-gate structure are proposed. Gate-all-around nanowire (GAA NW) MOSFET device is one of the most attractive structures. Besides, variability problems are becoming so crucial that they degrade the devices’ characteristic as well. Process variation effect (PVE), random dopant fluctuation (RDF) and work function fluctuation (WKF) are major fluctuation sources of all. In this thesis, exploring the influence of intrinsic characteristic fluctuation on GAA NW MOSFET with 10-nm-gate-length is conducted by full quantum mechanics theory and experimentally calibrated 3D quantum corrected device simulation. In the part of RDF, dopants penetrating from source/drain extension forms another unignorable fluctuation, which becomes more significant as the channel doping concentration decreases, so it must be included. The results show that the largest deviation of Vth is occurred as dopants are flocked at the place corresponding to the peak of conduction band profile regardless of RDF mechanism. In the part of PVE, the variations of gate length, radius, aspect ratio (AR) and oxide thickness are investigated. The results reveal that the fluctuation of oxide thickness is so small that it can be neglected, and the radius as well as aspect ratio (AR) have influential impact among all PVE factors. They have dependence on each other through a transformation formula. Although the device with large AR has poor SCE parameters, it has better suppression on PVE. Then RDF and PVE are combined to discuss the total impact. Small AR device has minimal fluctuation due to its own small effective radius, resulting in better channel controllability. In the part of WKF, the fluctuation is induced by the number and the location of metal grain with high work-function. The more metal grain with high work-function gathers near source side, the worse device’s characteristic is. Fabricating the size of metal grain which is far less than gate area can effectively reduce the characteristic fluctuation on device. Compared to tri-gate MOSFET, GAA NW MOSFET has great immunity to variation problems. As WKF and PVE are considered simultaneously, the device with small AR suffers more serious fluctuation, which is different from the trend of RDF. In summary, this thesis has discussed the impact of most important fluctuation sources on GAA NW MOSFET device. It provides semiconductor industry to develop some advanced device structures, materials and process technologies to promote the performance of chips.