探討碲化鉛奈米顆粒場效電晶體之電性

Abstract

電子在奈米顆粒自組裝薄膜中的傳輸行為，及其場效電晶體機制之探索，一直是重要研究題材。本實驗利用熱處理方式去除顆粒表面有機層，增加薄膜導電性並提升導電率。一般用基板背閘極電極來觀察碲化鉛奈米顆粒膜之場效開關比(on/off ratio)，約為1-2倍之間，變化不大。本實驗藉由製作上閘極電極，來探討其開關比及場效特性。利用高介電係數材料氧化鋁(ϵ~9.1，為常見的high k材料)，及採用氧化層30 nm厚度(相較於背閘極氧化層300 nm更薄的絕緣層)，鍍上上閘極電極產生之尖端電場效應來提高電場，預期提升開關比，在常溫300 K之下開關比可達10倍。此外，在低溫環境下，上閘極之開關比可達〖10〗^4~〖10〗^5倍，而背閘極僅達到大約〖10〗^1倍，顯然上閘極控制通道載子之效能確實獲得提升，因此開關比呈現懸殊的差距。在探討傳輸機制方面，發現擬合結果顯示出兩種傳輸機制，200 K以上之高溫區由nearest neighbor hopping傳輸主導，而200 K以下之溫區由ES hopping傳輸所主導，其傳輸機制轉折點與開關比隨溫度之轉折點相同，推測電子傳輸機制亦為影響開關比變化之因素。本實驗更利用碲化鉛場效電晶體設計三態邏輯元件，藉由上閘極與背閘極操作組合變化，展示出元件的操作及三種輸出狀態。

Electron transport in nanocrystal (NC)-assembled films is always an interesting topic. Here we employ PbTe NCs to study electron transport and field effects. Since the presence of capping ligands on NCs always leads to poor conductivity, we employ thermal treatment to reduce the capping. The on/off ratio of PbTe-nanocrystal field-effect transistor (FET) is usually of 1-2. In order to increase the on/off ratio, we use the top gate with high dielectric constant material 〖Al〗_2 O_3 and an oxide layer of 30 nm in thickness which is much thinner than the back gate oxide layer of 300 nm in thickness. On the other hand, the width of the top gate leads is small that can give higher electrical field and raise the on/off ratio of the FET device. The on/off ratio of top gate electrode reaches 10 at 300 K and it goes up to 〖10〗^5 at lower temperatures. However, the on/off ratio of back gate can merely approach 〖10〗^1 at lower temperatures. The top gate control for the channel carriers is exceedingly better than the back gate. From the investigation of transport mechanism, the nearest neighbor hopping (NNH) dominates at temperatures above 200 K and the Efros-Shklovskii (ES) variable range hopping dominates at temperatures below 200 K. The on/off ratio also exhibits the same transition temperature at 200 K as well. We thus confirm that the electron transport mechanism play an important role on the on/off ratio of the FET device. For the last part, we apply PbTe-nanocrystal FET to the demonstration of a tristate logic device. We combine both the top and the back gate to control output states so as to establish the operation of tristate logic device.