Title: | 適用於HEVC之快速移動估測演算法與硬體架構設計 Fast Algorithm and Architecture Design of Motion Estimation for HEVC |
Authors: | 張仲華 Chang,Chung-Hua 劉志尉 Liu, Chih-Wei 電子工程學系 電子研究所 |
Keywords: | 移動估測;高效率視訊編碼;motion estimation;HEVC |
Issue Date: | 2015 |
Abstract: | 高效視頻編碼(HEVC)是國際上的最先進的視頻編碼標準,相對於H.264 / AVC他提高了很大的壓縮效能,但其先進的技術,導致了高編碼複雜度。尤其是,移動估計(ME)在HEVC裡面就佔了50%以上的編碼時間。本文提出四種技術,以減少對HEVC計算複雜度。我們首先分析了先進移動向量預測(AMVP)的移動活率(motion activity)跳過非正方形預測單元(PU)的移動估計之計算。其次,我們創建了一個跳躍地圖(Skipping Map)跳過不必要的ME並且把移動向量(MV)設置為零。第三,我們採用了增強型十字-六邊形-內部搜尋演算法,以減少搜索點。第四,我們設定的碼率 - 失真成本(RD成本)臨界值在搜索中心提前終止ME計算。所提出的技術已經在實作HEVC參考軟體HM 10.0,實驗結果表明,約省下了97.96%的搜索點,而Bjontegaard失真率(BD-rate)只有上升0.6%。最後,我們設計了由3個核心整數移動估測引擎組成的硬體架構來實現我們的演算法。所提出的整數移動估測引擎是在TSMC 90nm製程實現的。總體移動估測架構採用了3個整數移動估測引擎,並且每個整數移動估測引擎的邏輯閘數目大約只有20.3K。最大操作頻率為238MHz,可支援4K×2K 30fps的即時視訊編碼。 High Efficiency Video Coding (HEVC) is the state-of-the-art video coding standard, which improves greatly compression performance relative to H.264/AVC, but its advanced techniques lead to high encoding complexity. Especially, the motion estimation (ME) in HEVC accounts for more than 50% encoding time. This thesis presents four techniques to reduce the computational complexity for HEVC. We first analyze motion activity of advanced motion vector prediction (AMVP) to skip the ME computations of non-square prediction units (PUs). Secondly, we create a skipping map to skip unnecessary ME and set zero to motion vector (MV). Thirdly, we employ an enhanced cross-hexagonal-inner search pattern to reduce search points. Fourthly, we set a rate-distortion cost (RD cost) threshold in search center to early terminate the ME computation. The proposed techniques have been implemented in HEVC reference software HM 10.0 and the experimental results show that approximately 97.96% of search points for ME are saved, while the Bjontegaard Distortion-rate (BD-rate) is only increasing by 0.6%. Finally, we design the hardware architecture composed of 3 cores IME engine to implement our proposed algorithm. The proposed IME engine is implemented by TSMC 90nm technology. Overall ME architecture employs 3 cores of the proposed IME engine and gate counts of each IME engine are only about 20.3K. The maximum working frequency is 238MHz, can supports 4Kx2K 30fps in real time video coding. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT070050228 http://hdl.handle.net/11536/126733 |
Appears in Collections: | Thesis |