微處理器之低漏電耗能迴圈分割方法

Abstract

隨著現代半導體製程技術的進步，漏電功耗已成為一向值得被關注的議題，因此許多研究開始在硬體與軟體上發展節省漏電耗能的技術。電源閘控（Power-Gating）是一項有效的硬體省電技術，該技術將閒置的電路元件切換至低功耗模式，以達到節省漏電耗能的效果。 然而，由於功能單元（Functional unit）的使用分佈分散於整個程式中，導致功能單元的閒置時間區段過短，使得電源閘控應用於功能單元的效果不彰。在這份研究中，我們提出低功耗迴圈分裂架構於編譯器之上，意圖集中在迴圈結構中，功能單元的使用分佈，藉此延長功能單元的閒置時間，已增加更多利用電源閘控減省漏電耗能的機會。本研究採用 0-1 二次規劃 （Binary quadratic programming），依據功能單元的需求狀況，將迴圈體分割成多個迴圈。 本研究提出的架構實作於 GNU 編譯器 （GNU compiler collection），並使用 sim-panalyzer 模擬並測量效能與耗電。實驗結果表明，我們提出的架構可有效地減少功能單元的漏電耗能，同時不會造成顯著效能損失。

With the advances in modern semiconductor technologies, leakage power has become an issue of concern. Many researches have proposed hardware and software techniques to reduce leakage energy. Power gating is an effective technique that turns idle components into low-power mode to reduce leakage energy at the hardware level. However, the distribution of functional unit usage is often scattered within a program, and it is unfavorable to apply power gating to functional units, the idle time period of which is fragmented into short idle fragments. In this thesis we attempt to cluster the distribution of functional unit usage within loops so as to extend the idle durations of functional units and thereby to increase the opportunity for energy saving. We present an energy-aware loop transformation framework for a compiler to generate distributed loops on leakage energy considerations. Our framework provides a binary quadratic programming (BQP) model that attempts to divide a loop body into several loops, with each loop having different functional unit requirements. We have incorporated our proposed framework into the GNU compiler collection (GCC) and simulated performance and energy consumption using sim-panalyzer. The experimental results demonstrate that our framework was effective in reducing the energy consumption of functional units without significant loss of performance.