标题: 氮化矽侧壁硬式光罩制造之环绕式闸极多晶矽无接面奈米线薄膜电晶体特性研究
Characterization of Gate-All-Around Nanowire Junctionless Poly-Silicon Thin Film Transistors Fabricated by Nitride Hard Mask Methods
作者: 简崇哲
Chien, Chung-Che
林鸿志
黄调元
Lin, Horng-Chih
Huang, Tiao-Yuan
电子工程学系 电子研究所
关键字: 奈米线;无接面;薄膜电晶体;多晶矽;Nanowire;Junctionless;TFT;Poly-Silicon
公开日期: 2015
摘要: 在本篇论文中,成功利用氮化矽侧壁硬式光罩(nitride-spacer hard mask)的方式,仅藉由I-Line微影技术即可有效制作高度微缩之电晶体,其中通道长度可微缩至200奈米以下,并可达到15奈米的奈米线(nanowire)宽度。本文并使用同步掺杂之低压化学气相沉积形成多晶矽无接面电晶体之高掺杂浓度通道。由于环绕式闸极(Gate-All-Around)的形成,可由低于100 mV/dec的次临界摆幅显示出良好的闸极控制能力。另外,本文中亦利用Pelgrom Plot来探讨临界电压之变异。在有效微缩的元件中,可量得清晰的二层级随机电报杂讯(2-level random telegraph noise)并进行分析。我们并由量测之信号萃取不同偏压条件下的特性常数,包含在数毫秒范围变化的时间常数,以及萃取之随机电报杂讯振幅,得以清楚研究二层级随机电报杂讯的行为。
In this thesis, effectively scaled poly-Si nanowire (NW) junctionless (JL) devices were formed by nitride hard mask methods simply with I-Line lithography. In the fabrication, in-situ doped poly-Si deposited by LPCVD is adopted to serve as the heavily-doped channel of JL devices. Devices with channel length shorter than 200 nm and NW width around 15 nm have been successfully fabricated. The steep SS lower than 100 mV/dec is achieved owing to the good gate controllability by the gate-all-around structure. The Pelgrom plots are made to analyze and discuss the threshold voltage fluctuation. We also observe clear 2-level RTN characteristics in our scaled devices. RTN time constants are extracted to be around a few milliseconds, and dId/Id
are analyzed to probe the switching properties between discrete levels at different bias conditions.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT070250142
http://hdl.handle.net/11536/127020
显示于类别:Thesis