完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 陳秋豪 | en_US |
dc.contributor.author | Chen, Chiu-Hao | en_US |
dc.contributor.author | 黃中垚 | en_US |
dc.contributor.author | Huang, Jung-Yao | en_US |
dc.date.accessioned | 2015-11-26T01:02:05Z | - |
dc.date.available | 2015-11-26T01:02:05Z | - |
dc.date.issued | 2015 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT070250571 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/127177 | - |
dc.description.abstract | 隨著尺寸微縮,鑲嵌式電晶體已經越來越盛行。而在鑲嵌式線路中,非揮發性記憶體已經越來越成熟並且成為傳統DRAM的強力競爭對手。它的優點在於沒有電源時,資料仍然能存在裡面,因此功耗較低。藉由高介電常數介電質的開發,電荷儲存記憶體的效能和可靠度也能更加進步。 隨著高介電常數介電質的開發,越來越多應用到電荷儲存記憶體上,使他成為快閃記憶體的明日之星。這篇論文介紹高介電常數介電質應用在電荷儲存記憶體上。根據之前學長們的基礎,我們把阻擋層替成高借電系數的氧化鋁。其中不同溫度以及不同瓦數氧化鋁的品質我們藉由沉積速率、等效氧化厚度、介電常數、色散、以及材料分析的方法來鑑定。雷射系統,對於低溫製程也是很重要的一環,也會在這篇論文中被討論。兩種不同介電層材料的記憶體特性,包含寫入抹除速度,電荷保持力,受偏壓破壞測試的結果都會被討論到。同時,這些特性在不同溫度下對溫度的結果也會被討論到。藉由雷射和電漿輔助原子層沉積之能帶工程介電閘極製作的記憶體,不但可以在低溫製程下完成,他也能得到好的效能和可靠度。 | zh_TW |
dc.description.abstract | Recent trends of scaling have led to prosperity of embedded application. Non-volatile memory, featuring stored information can be retained in the absence of power, has become a promising alternative for conventional DRAM. With high-K dielectrics introduced, reliability and performance improvement can be achieved. Charge trapping memory is regarded as one of the most promising flash memory technologies as further down-scaling continues. In addition, more and more exploration is investigated with high-k dielectrics implemented in the charge trapping memory. This thesis reviews the advanced research concerning charge trapping memory with high k dielectrics employed. On the basis of preceding research, we have now improved and substituted aluminum oxide for silicon oxide. Various process temperature as well as power are demonstrated and examined by means of permeability (abbreviated as K), dispersion and other material analysis techniques. Laser activation, which is essential to low thermal budget embedded application, has been discussed in this thesis. Two stacking dielectric structures along with retention and endurance characteristics are investigated. Temperature dependence of these characteristics will be investigated as well. For further investigation, we may introduce our hafnium oxide, which is examined by permittivity and other material analysis techniques, to our dual tunneling NVM as charge trapping layer. Hence, larger hysteresis can be expected. With laser and plasma enhanced ALD, low thermal budget NVM with decent performance and reliability can be accomplished. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 電漿輔助原子層沉積 | zh_TW |
dc.subject | 能帶工程介電閘極 | zh_TW |
dc.subject | 電荷儲存式非揮發性記憶體 | zh_TW |
dc.subject | Plasma Enhanced atomic layer deposition | en_US |
dc.subject | band-gap engineered gate structures | en_US |
dc.subject | Charge Trapping Non-volatile Memory | en_US |
dc.title | 以電漿輔助原子層沉積之能帶工程介電閘極製作高可靠度電荷儲存式非揮發性記憶體 | zh_TW |
dc.title | Reliable Charge Trapping Non-volatile Memory by Plasma Enhanced atomic layer deposition-fabricated band-gap engineered gate structures | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 光電工程研究所 | zh_TW |
顯示於類別: | 畢業論文 |