60GHz FBMC 基頻接收器之符元間干擾與載波間干擾抑制等化器

Abstract

這篇論文審視濾波器組多載波(FBMC)傳輸系統與其特性。一般而言FBMC不使用循環字首，造成他對多路徑符元間干擾非常敏感。在這觀點之下，此論文首先針對時域等化器與最小均方誤差之頻域多階等化器於符元間干擾存在的FBMC系統中進行效率比較與討論。隨後將提出一個抑制FBMC在長多路徑通道中遭遇到的符元間干擾與載波間干擾的最小均方誤差複合式反饋前饋等化器 (MJFFE) 。 MJFFE等化器的係數計算方式也會呈現出來。 以上所提的三個等化器在濾波器組多載波系統中模擬時將參照著IEEE 802.15.3c的框架架構與非直視性多路徑通道。此多路徑通道平均的方均根延遲擴展是3.4ns，而取樣率為2.64GHz. 模擬結果顯示先行時域等化器與頻域多階等化器在高分散性的多路徑通道中表現的並不好。提出的MJFFE反而能夠比一階頻域等化器低0.6dB的訊雜比時通過10-2 誤碼率的界線。另外跟一階頻域等化器相比，MJFFE還明顯的降低了誤碼率的地板效應。因為MJFFE需要複雜的係數運算，所以經由時序共用、記憶體共用與計算單元共用，整個MJFFE的複雜度減少了約50%。 MJFFE藉由台積電40奈米泛用製程資料庫建置後，其面積為1.335 mm2 或等效 1882k邏輯閘，估計的功耗在IEEE 802.15.3c框架中為50mW，考慮21.4Gbps的資料傳輸率，單位傳輸率所耗的能量為2.6pj/b。

This thesis reviews the FBMC transmission system and its characteristics. Conventionally the FBMC waveform do not make use of the cyclic prefix, which makes it vulnerable to multipath ISI. In view of this, the time domain equalizer and the frequency domain minimum mean square error (MMSE) multi-tap equalizer is reviewed for their ability to perform equalization in the presence of ISI for an FBMC system. The MMSE joint feedback feed-forward equalizer (MJFFE) is proposed to deterministically suppress the ISI and ICI suffered by the FBMC in a long multipath channel. A coefficients calculation method for the MJFFE is also presented. The three equalizers mentioned above are simulated with the FBMC system, with IEEE 802.15.3c frame structure in NLOS multipath channels that is generated from channel models provided for the IEEE 802.15.3c standard. The average RMS delay spread of the simulated multipath channel is 3.4ns, while the sampling rate is 2.64GHz. Simulation results show that the time domain equalizer and the frequency domain MMSE multi-tap equalizer do not perform well in the highly dispersive multipath channels. The proposed MJFFE is able to achieve the 10-2 bit error rate threshold at SNR that is 0.6dB lower than that of a frequency domain one-tap zero-forcing equalizer. Compared to the one-tap zero-forcing equalizer, the MJFFE also significantly lowers the BER error floor. The MJFFE has very high computation complexity due to the complicated coefficients calculation method. By using time multiplexing, memory sharing and computing element sharing methods, the complexity of the whole MJFFE system is reduced by approximately 50%. The MJFFE system is then implemented with the TSMC 40nm general purpose standard cell library at worst case conditions and temperature of 125C. The final area and gate count is 1.335 mm2 and 1882k respectively. The estimated power consumption operating in the IEEE 802.15.3c frame is 50mW, which translates to 2.6pJ/b.