佈局最佳化的低壓元件堆疊來達成高壓積體電路之靜電放電防護設計

Abstract

靜電放電防護和閂鎖效應 (latchup) 預防是在積體電路中兩個重要的可靠度議題，尤其是在高壓應用方面。靜電放電可能發生在積體電路產品製造、封裝、組裝的過程中，通常會造成在積體電路中嚴重的損害，而在電路正常操作情況下，雜訊可能會觸發積體電路內部的寄生電晶體，所以在高壓靜電放電防護設計中，必須使持有電壓 (holding voltage) 高於電路操作電壓，否則在應用上可能會發生閂鎖效應 (latchup)。 高壓的靜電防護設計中，通常使用橫向擴散電晶體 (lateral diffused MOS, LDMOS)，但通常橫向擴散電晶體的持有電壓小於電路的操作電壓，會有閂鎖效應的風險，因此提出使用低壓電晶體來做堆疊結構來達到在高壓中靜電防護有著高持有電壓的一種方法，藉由調整元件的不同堆疊個數，使得在不同高壓應用來提供有效的靜電防護。 在此篇論文中，實驗並驗證堆疊結構，藉由多種不同的佈局方式來增加元件的靜電耐受度，並且使用不同的防護環 (guard-ring) 的佈局方式，探討對持有電壓的影響。此外，使用不同傳輸線脈衝產生器 (transmission line pulsing, TLP) 脈衝寬度對持有電壓的影響，以及試著減少其佈局面積達到相同的靜電耐受度。

Electrostatic discharge (ESD) protection and latchup prevention are two important reliability issues to the CMOS integrated circuits, especially in high-voltage (HV) applications. ESD may occur accidentally during the fabrication, package, and assembling processes of IC products, which often caused serious damages on ICs. During normal circuit operation, the noise might unpredictably trigger the parasitic BJT of the ESD devices. Furthermore, to avoid latchup issue, the holding voltage (Vh) should be larger than the supply voltage of the internal circuits in ESD protection design for HV applications. Lateral DMOS (LDMOS) was often used as ESD protection device in HV process, but the holding voltage (Vh) of LDMOS after snapback was smaller than the circuit operating voltage (VCC). Thus, the LDMOS was sensitive to latchup issue. Therefore, the stacked configuration of LV devices is a way to achieve a high holding voltage for ESD protection in HV circuits. By adjusting the stacking numbers of stacked PMOSs, it can provide effective ESD protection for various HV applications. In this thesis, stacks for ESD protection are implemented and verified, and it is discussed about different layout parameters to effectively improve ESD robustness of ESD devices. The guard-ring layout on the stacked LV devices was further investigated holding voltage in silicon chip. In addition, the pulse width of the transmission line pulsing (TLP) system was also investigated holding voltage in silicon chip. Decreasing the layout area to get high ESD robustness and latchup-free immunity for HV applications.