Full metadata record
DC Field | Value | Language |
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dc.contributor.author | 王元鼎 | en_US |
dc.contributor.author | Wang, Yuan-Ding | en_US |
dc.contributor.author | 莊紹勳 | en_US |
dc.contributor.author | 汪大暉 | en_US |
dc.contributor.author | Chung, Shao-Shiun | en_US |
dc.contributor.author | Wang, Ta-Hui | en_US |
dc.date.accessioned | 2015-11-26T01:02:27Z | - |
dc.date.available | 2015-11-26T01:02:27Z | - |
dc.date.issued | 2015 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT070250178 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/127431 | - |
dc.description.abstract | 隨著製程世代不斷的微縮,臨界電壓的控制成為了一項重要的問題並且其中有著許多先天上難以克服的缺點,如隨機摻雜擾動(Random Dopant Fluctuation)、線邊粗糙度(line edge roughness)、功函數變異(Work Function Variation)。上述大部分的問題經過製程的優化以及元件幾何的改變(FinFET)之後都將會得到改善。然而,功函數變異的改善卻有限,當製程技術達到10奈米世代時,功函數變異將會主導臨界電壓的擾動。為了要了解以及改善此問題,已經有許多文獻探討了金屬結晶導致的功函數變異,但是其實介面偶極以及氧化層缺陷也會影響功函數。而在本論文中,吾人將探討介面偶極以及氧化層缺陷在高介電質氧化層中對功函數變異的影響。 首先,我們推導出可以直接計算功函數變異的公式,另外為了要更深入的了解,利用多變數分析把功函數變異分解成三個變數因子Vth、VFB 以及VOX。藉由多變數分析,此方法可以清楚地並且分別了解在n型以及p型金氧半場效電晶體中主導功函數變異的因子為何,並且經由上述結果,提出了一項簡單的實驗方法可以用來分離在金屬閘極/高介電氧化層(MG/HK)以及高介電氧化層/介面層(HK/IL)中的偶極。再者,為了要抑制功函數變異,我們也探討如何藉由改變TiN吸附層中氮濃度來降低功函數變異以及其機制探討。 其次,我們將利用上一章節的方法,用來探討、分析並且比較偏壓溫度不穩定性前後所引起的功函數變異的不同。另外,功函數變異的來源同時也會對臨界電壓有所影響,為了要考慮高介電質氧化層偶極以及氧化層缺陷所導致的臨界電壓變異,我們類似Pelgrom plot,提出等效氧化層厚度做歸一得到新的斜率Evt,利用此斜率,高介電質氧化層偶極以及氧化層缺陷的影響即可被正確的判斷出來。 | zh_TW |
dc.description.abstract | With the continuous technology node scaling, the control of threshold voltage becomes a serious problem. There are several inherent disadvantages that are difficult to overcome, such as random dopant fluctuation, line edge roughness, and work function fluctuation. Most issues describe above will be improved via process advances or the change of devices geometry (e.g., FinFET). However, the improvement of work function fluctuation by these methods is limited because of the metal grain will become as small as critical length, there are only few grains when devices scale down to 10nm, finally, WFV(Work Function Variation) will dominate the Vth fluctuation. In order to solve these problems, lots of papers have investigated metal grain induced WFV, but the interfacial dipole also affects WFV based on basic device physics. In this thesis, we will investigate the interfacial diploes and bulk traps which affect WFV in HKMG stacks First, we derive the equation which can calculate WFV directly. Further, we do the multi-variant analysis MVA) to decuple the WFV into Vth, VFB and VOX. By the MVA, the major variance source can be clearly realized in n- and p-MOSFET respectively. Based on MVA result, we proposed a simple experimental method to separate the effect of interfacial dipole between MG/HK and HK/IL. Furthermore, to suppress WFV, TiN adhesion layer with different nitrogen concentration and the mechanism have been discussed. Next, BTI stress induced WFV will be discussed. After the stress, the same analytical method has been used and the change of WFV before/after BTI stress has also been compared. Moreover, in order to include the effects of WFV on Vth variation induced by HK dipoles and traps, a new Evt plot is proposed by normalizing Pelgrom plot with the electrical oxide thickness. | en_US |
dc.language.iso | zh_TW | en_US |
dc.subject | 高介電氧化層 | zh_TW |
dc.subject | 介面偶極 | zh_TW |
dc.subject | 功函數變異 | zh_TW |
dc.subject | 氧化層缺陷 | zh_TW |
dc.subject | 偏壓溫度不穩定性 | zh_TW |
dc.subject | 互補式電晶體 | zh_TW |
dc.subject | high-k dielectric | en_US |
dc.subject | interfacial dipole | en_US |
dc.subject | work function variation | en_US |
dc.subject | oxide trap | en_US |
dc.subject | bias temperature instability | en_US |
dc.subject | CMOS | en_US |
dc.title | 高介電層金屬閘極CMOS電晶體功函數與臨界電壓變異之關聯性探討 | zh_TW |
dc.title | New Understandings on the Correlation Between Work-function Fluctuation and Vth Variation in HKMG CMOS Devices | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子工程學系 電子研究所 | zh_TW |
Appears in Collections: | Thesis |