因應電路微幅更新之快速的時序與時脈樹悲觀性分析

Abstract

靜態時序分析是現今 IC 設計中用來驗證時序收斂的一個關鍵步驟。然而，隨著快速成長的設計複雜度以及晶片上的變異，靜態時序分析因而更加複雜。為了更精準地分析時序性能，共同路徑悲觀性移除是普遍用來修正在時序路徑上透過時序分析產生的過度悲觀的結果。同時，在設計的過程中設計者往往需要不斷的更改設計來達到設計上的要求，如何在設計變動後快速的更新時序資訊成了 IC 設計中重要的問題之一。 為了減少在變動設計間不斷更新時序的次數，我們提出了一個有效且快速的時序分析架構，採用以節點為基礎的靜態時序分析，並提出變動性時序更新、動態阻擋、支配以及優先搜尋最差路徑。實驗結果顯示我們提出的方法可以有效的減少時序更新以及搜尋時序路徑的次數，並且和 TAU2015 的競賽結果相比，可以達到超過 1.7 倍的加速效果。

Static timing analysis is a key step to verify timing closure for modern IC designs. However,fast growing design complexities and increasing on-chip variations complicate this process.To capture more accurate performance of a design, common path pessimism removal is prevalent to eliminate artificially induced pessimism in clock paths during timing analysis.Furthermore,designer continuously changes part of design during flow for reaching target performance.It becomes an significant problem updating timing incrementally during IC design. To reduce updating rates during design changing, we present an efficient timing analysis framework aiming at updating timing incrementally and removing common path pessimism. This framework is based on block-based static timing analysis, incremental updating, dynamic shielding, dominance and worst-slack-first path retrieval. Experimental results show that the proposed method significantly reduces the numbers of timing updating and path retrieval. Furthermore, our approach has better performance comparing with TAU 2015 timing contest winners, achieving more than 1.7X speed-ups.