以二維晶粒成長技術製作具類單晶矽之薄膜電晶體之特性研究

Abstract

高性能低溫多晶矽薄膜電晶體是在低成本玻璃基板上製作高品質之主動式有機發光二極體顯示器(AMOLEDs)，全功能整合系統面板(System-On-Panel)以及三維積體電路(Three-Dimensional Integrated Circuits)之關鍵元件。準分子雷射結晶(Excimer Laser Crystallization)對非晶矽薄膜進行再結晶，可在低溫形成具高結晶性之矽晶粒以達成較佳之元件特性。然而，對於傳統的低溫多晶矽薄膜電晶體相較於絕緣體上矽結構元件而言仍然有著比較低的載子遷移率以及比較差的元件對元件之均勻性，因為晶粒邊界仍然任意分布於通道區域。因此，我們需要一個更進階的準分子雷射結晶法去大幅的提升晶粒尺寸及精確的控制晶粒邊界的位置。 在本篇論文中，我們所提出的準分子雷射結晶法是基於凹陷形通道的矽條狀(Recessed-Channel Si Strip, RCS)結構搭配氮化物底層(Under-Layered Nitride, ULN)而成的RCS-ULN結構來實現，此方法能被使用來達成二維側向晶粒成長。根據之前的報導而引入具有高光吸收係數之氮化物薄膜作為底層，使得沿著垂直矽條狀方向之側向溫度梯度呈現較高溫於矽條狀之邊緣而較低溫於條狀之中央，所以平行於矽條狀之晶粒邊界在施打準分子雷射後被去除。此外，透過凹陷形通道結構產生沿著平行矽條狀方向之側向溫度梯度，所以晶粒是從厚區開始延伸至薄區成長。然後，我們將仔細的討論準分子雷射能量密度效應 (E)、厚區長度效應 (L)、凹陷形通道長度效應 (R)以及凹陷形通道寬度效應 (W) 對於RCS-ULN結構上的矽結晶行為。經過有系統性的研究，我們發現利用RCS-ULN結構搭配 E ≧ 380 mJ/cm2、L ≧ 1.2 μm、R ≦ 2.0 μm 以及W ≦ 0.7 μm能夠有最佳化的晶粒結構，此結構有著兩個乾淨側向成長的大晶粒且產生單一晶粒邊界位於凹陷形區域之正中央處。 然後，為了要進一步了解在RCS-ULN薄膜電晶體上位於中央處之晶粒邊界效應，將會研究當不同的位移距離(Dshift)遠離位在凹陷形區域中央處之晶粒邊界。因此，RCS-ULN薄膜電晶體在其Dshift = 0.4 μm且通道長度為0.5 μm、E ≧ 380 mJ/cm2、L ≧ 1.2 μm、R = 2.0 μm以及W = 0.5 μm，其相較於顯示出絕佳的場效載子應遷移率高達613 cm2/V-s且開關電流比高達5.51 × 108，而傳統的薄膜電晶體之場效載子移動與開關電流比分別為146 cm2/V-s 與1.59 × 108，這是歸因於在以上這樣的條件下有類單晶矽位於通道區域 中。此外，RCS-ULN薄膜電晶體搭配Dshift = 0.4 μm相較於其搭配Dshift ≦ 0.2 μm而言，能獲得明顯的改善在元件之均勻性。 總之，以二維晶粒成長技術製作類單晶之RCS-ULN薄膜電晶體被成功製備，此技術相當適合應用於未來之系統面板與三維積體電路等相關領域。

High-performance low-temperature polycrystalline-silicon (LTPS) thin-film transistors (TFTs) are key devices for the applications in the high-quality active-matrix organic light-emitting displays (AMOLEDs), full-function system-on- panel (SOP), and three-dimensional integrated circuits (3D-ICs). Excimer laser crystallization (ELC) of amorphous silicon (a-Si) can produce high-quality silicon thin films with large grains at low temperatures to attain the superior device performances. As compared with the silicon-on-insulator (SOI) devices, however, the mobility was still low and the device-to-device uniformity was bad for the conventional LTPS TFTs since the grain boundaries still randomly distributed in the channel region. Therefore, an advanced ELC method is necessary to enhance the grain size and precisely control the grain boundary location. In this thesis, an ELC method based on the recessed-channel Si strips (RCS) structures with the under-layered nitride (ULN) film, which is named as the RCS-ULN structures, has been proposed to achieve the two-dimensional (2-D) lateral grain growth. According to the previous report, the lateral temperature gradient along the direction perpendicular to the Si strip appeared to be higher for the edge region of the Si strip than that for the middle one via the employment of the under-layered nitride film with a high light absorption coefficient so that the grain boundaries parallel to the Si strip could be eliminated during the ELC. Moreover, the lateral temperature gradient along the direction parallel to the Si strip was produced by using the recessed-channel structures so that the grains originated from the thick regions extended to the thin recessed region. Furthermore, the effects of the ELC energy density (E), the thick-region length (L), the recessed-channel length (R), and the recessed-channel width (W) on the Si crystallization for the RCS-ULN structures have been also discussed in detail. With a systematical research, we found that the best structure with two single-grain-like grains in the recessed region and only one perpendicular grain boundary located at the middle of the recessed region could be formed by employing the RCS-ULN structures with E ≧ 380 mJ/cm2, L ≧ 1.2 μm, R ≦ 2.0 μm, and W ≦0.7 μm. Then, to further realize the effect of the middle grain boundary on the RCS-ULN TFTs, various shift distances (Dshift) away from the middle grain boundary in the recessed region have been investigated. As a result, the RCS-ULN TFTs with the channel length of 0.5 μm, E ≧ 380 mJ/cm2, L ≧ 1.2 μm, R = 2.0 μm, and W = 0.5 μm exhibited an excellent field-effect mobility as high as 613 cm2/V-s and a high on/off current ratio of 5.51 × 108 for the ones with Dshift = 0.4 μm as compared with 146 cm2/V-s and 1.59 × 108 for the conventional ones, respectively. It is attributed to the single-grain-like Si in the channel region for such a condition. In addition, the RCS-ULN TFTs with Dshift = 0.4 μm also attained much improvement in the device uniformity as compared with TFTs with Dshift ≦ 0.2 μm. In summary, the single-grain-like RCS-ULN TFTs via the 2-D grain growth technology have been successfully demonstrated. It is thus promising for the future applications in the LTPS TFTs in system-on-panel (SOP), 3D-ICs, and so on.