標題: A 28mW OFDM Baseband Receiver Chip for DVB-T/H with All Digital Synchronization
作者: Wei, Ting-Chen
Liu, Wei-Chang
Tseng, Chi-Yao
Long, Syu-Siang
Jou, Shyh-Jye
Shiue, Muh-Tian
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2008
摘要: An OFDM baseband receiver chip for DVB-T/H application is proposed in this paper. With all-digital jointed detection/synchronization loops and channel estimation, the proposed receiver chip can compensate 200ppm sampling clock offset (SCO) and +/- 50 subcarrier spacing carrier frequency offset (CFO) in multipath environment The total memory requirement of this chip is 102.8KB and the total equivalent gate count (including memory) is about 806,800 gates. By using 0.18 mu m CMOS process, the power consumption is 28mW at 1.45 V, 40MHz and core size of this chip is 3600 mu m x 3600 mu m.
URI: http://hdl.handle.net/11536/1275
ISBN: 978-1-4244-2018-6
期刊: PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE
起始頁: 351
結束頁: 354
顯示於類別:會議論文