決定奈米尺寸場效電晶體之有效通道長度與源/汲極串聯電阻的先進方法

Abstract

大多數萃取有效通道長度及源/汲極串聯電阻(RSD)的方法都無法適用於現今的元件。透過閘極穿隧電流的量測與分析，我們提出一個精準的方法來決定閘極與極源/汲極重疊長度(L)，並以此改善源/汲極串聯電阻與有效通道長度不可分離的難題。借由已知的L，得以減少受到實驗誤差的影響。此外探討了L及RSD對於實驗量測的電子遷移率之準確性的影響。 在考慮閘極與極源/汲極重疊長度後，得到修正的閘極穿隧電流密度和基極電流密度。成功利用雙層介電質模型模擬金屬閘高介電n型金氧半場效電晶體閘極電子穿隧電流。並發現由於氧的缺乏而引起界面缺陷能提供額外的穿隧路徑。引入此效應後，得以吻合量測的基座電流密度。

Several methods of determining effective channel length (Leff) and source/drain series resistance (RSD) are not applicable to modern devices. According to our measurement and analyses of gate tunneling current, we propose an accurate method to determine gate to source/drain extension overlap length (L), while overcoming the inseparability issue in the source/drain series resistance extracting. With the known L, we can reduce the influence of the experimental errors. Moreover, we discuss the effects of extracted L and RSD on the accuracy of the experimentally determined inversion-layer mobility. With considering L, we can properly determine the gate and substrate current density. We successfully reproduce the measured gate conduction-band electron tunneling current in high-k metal gate nMOSFET by a dual-dielectric-layer model. We also discover that the presence of the interfacial states induced by the oxygen vacancies can provide extra tunneling paths. By introducing such effect, our proposed model can fit well the experimental substrate current density or equivalently the valence-band electron tunneling current.