應用於邏輯線路之低耗能三閘極砷化銦高電子遷移率電晶體之研究

Abstract

近年來，次微米級線寬的平面電晶體已經成為半導體工業的主流，許多研究仍然致力於縮小閘極寬度。但隨著元件尺寸的縮小，有些問題會愈發明顯，例如閾值電壓絕對值增加以及漏電流上升等短通道效應。因此，為了更進一步提升元件特性，尋找新的通道材料或研發新的製程方法都是可行的。 由於三五族的砷化銦材料與磷化銦基板晶格匹配，以及具有高電子遷移率和低閾值電壓，因此在此研究中，我們使用砷化銦通道高電子遷移率電晶體提升電子傳輸速度與低耗能下的邏輯特性。此外，透過兩次電子束微影以及蝕刻技術，在此研究中成功的使通道和閘極形成立體結構，即三閘極電晶體，有效地增加閘極與通道之間的接觸面積。此研究也比較了立體與平面結構電晶體之間的電性差異。 結果顯示三閘極電晶體比平面電晶體在低偏壓下(VDS=0.5V)具有更好的邏輯特性，元件展現了較低的次臨界擺幅、較低的漏電流與較大的開關電流比，而當偏壓上升至VDS=1V時，元件的次臨界特性以及開關比又有更進一步的改善。由這些研究結果可以證實，三閘極砷化銦通道高電子遷移率電晶體極有潛力作為未來後矽半導體世代高速邏輯電晶體的使用。

Recently, the planar transistors with sub-micro-scale gates have already been the trend of semiconductor industry. Many researches still focus on reducing gate length. However, as the transistor scales down, many problems start appearing, such as VTH roll-off and off-state leakage, or so called short channel effect. Therefore, searching a new channel material and a corresponding fabrication process are urgent to improve the device characteristics. InAs channel lattice possesses with high electron mobility and low threshold voltage. It matches with InP substrate as well. As a result we use InAlAs/InAs/InP high electron mobility transistors (HEMTs) to achieve high-speed and low power consumption in this study. Furthermore, by double Electron beam lithography and etching, 3-D structure HEMTs that increase the area between gate and channel has been successfully fabricated. This study also compared electrical characteristics between 3-D and planar devices. The results show that the 3-D devices present better logic parameter, including lower subthreshold swing(SS), lower off-state leakage current and larger Ion/Ioff ratio for low power logic applications(VDS=0.5V). When VDS increases to 1V, the subthreshold characteristics and Ion/Ioff ratio are further improved. These results demonstrate Tri-Gate InAs HEMTs are suitable for high-gain, low noise and low voltage applications.