閘極調控之奈米線蕭特基二極體之電性研究

Abstract

近年多重閘極結構場效電晶體以及蕭特基二極體被廣泛的研究，目的是為了得到性能更好、耗能更低的元件。先進製程使現今元件也往微小化邁進，以奈米線作為元件通道的微縮目標可以達到較高體表面積比以提升奈米線通道對於閘極電位改變的靈敏度。本研究以利用I-line的微影光源(365nm)與側壁(sidewall)spacer方法，成功製作出截面積3553奈米的矽奈米線，在奈米線上以三面閘極(trigate)作為奈米線蕭特基二極體之控制閘極。配合先進微電子製程的考量之下，本研究選用鎳矽化合物(Nickel-silicide)作為金屬與半導體之間形成蕭特基接面的金屬材料。鎳在矽奈米線中的介面與擴散行為則透過掃描式電子顯微鏡(SEM)進行分析，並且利用能量色散X射線光譜(EDS)進行定性分析。本研究製作出的n-type蕭特基接面元件在電流電壓的特性上，皆有因為受到閘極電壓的施加而改變了電流的特性，不論是以400 mV的閘極電壓差，亦或是50 mV的閘極電壓差，在蕭特基二極體逆向偏壓操作時，皆有明顯的電流變化，而其對閘極電壓感應極限約為10 mV。閘極對於金屬/半導體蕭特基二極體元件載子傳輸之影響也在本論文探討。從實驗電性結果推測，如果能將介面缺陷透過製程的改善來降低，則矽奈米線蕭特基接面元件可以成為靈敏感測閘極表面電為變化的元件，在未來可以與延伸式閘極搭配，可作為一靈敏的即時感測元件。

In recent years, multiple gate structure field effect transistor and Schottky diode have been widely studied in order to boost the electrical abilities of the semiconductor devices for low-power applications. As a result of high surface-to-volume ratio, the scaling of the channel of modern electronic device to nanometer size enhances the sensitivity of electronic device to the gate voltage. In this thesis, we fabricated silicon nanowire with 3553 nm cross-section via I-line and side wall spacer technique. The nanowire was then wrapped with trigate structure. After the formation of gate, nickel silicidation was performed along the channel of silicon nanowire to form a metal-semiconductor junction under the gate. Material characterizations of this gate-controlled Schottky diode were performed by SEM, TEM and EDS. The discussion of carrier transport behaviors under the gate biases is also included. The Electrical characteristics of the gate-controlled Schottky diode exhibits that both 400 mV and 50 mV gate bias induce effective current changes at the reverse bias. The limitation of gate bias sensitivity is about 10 mV. If the defects at gate/channel interface can be further minimized, the Schottky diode can be a sensitive device to gate potential change