混合穿隧式場效電晶體與鰭式場效電晶體的高效能32位元前瞻進位加法器與閂鎖電路超低壓應用之研究與分析

Abstract

本論文研究混合穿隧式場效電晶體與鰭式場效電晶體之32位元前瞻進位加法器與閂鎖電路。我們使用三維TCAD混合模式模擬器模擬電晶體特性，並利用與TCAD模擬結果校準過之HSPICE查表式Verilog-A模型進行電路模擬。進一步將處於近臨界區的混合式電路之延遲、動態功率/能量、漏電功耗與功耗延遲乘積/能量延遲乘積與皆使用穿隧式場效電晶體以及皆使用鰭式場效電晶體的電路做比較。

針對混合式32位元前瞻進位加法器而言，第一關鍵路徑使用穿隧式場效電晶體以減少的最長路徑之延遲，並且在電路的其餘部分使用鰭式場效電晶體，以減少開關功率和漏功率之損耗。在VDD = 0.3伏特附近，相較於都使用鰭式場效電晶體與都使用穿隧式場效電晶體之電路，混合式32位元前瞻進位加法器的功耗延遲乘積較好(小)。在考慮到功函數變異（WFV）與線邊緣粗糙度（LER）後，當電壓在0.3伏特時，與都使用鰭式場效電晶體與都使用穿隧式場效電晶體之電路相比，混合式電路實現之功耗延遲乘積的變異特性是具有可較性的。

針對混合式閂鎖電路（包括SCCL，LVCL，MTLP和PTL）而言，關鍵路徑上使用穿隧式場效電晶體被來降低電路延遲，且鰭式場效電晶體被用於電路的其餘部分以減少功率消耗。相較於與都使用穿隧式場效電晶體之電路，混合式閂鎖電路提供相當或更短的電路延遲且同時具有優異的能量延遲乘積。當這四種類型的閂鎖電路操作在低電壓下（<0.30伏特），混合式LVCL在電路延遲與能量延遲乘積方面有顯著的改進。在考慮到功函數變異與鰭線邊緣粗糙度後，當電壓在0.25伏特時，相較於都使用鰭式場效電晶體與都使用穿隧式場效電晶體之電路，混合式電路實現之能量延遲乘積的變異特性是具有可較性甚至更好的。

In this thesis, we investigate the hybrid TFET-FinFET implementation of 32-bit carry-look-ahead adder (CLA) and latch circuits using atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The circuit delay, dynamic power/energy, leakage power and power/energy-delay product (PDP/EDP) for hybrid implementations are compared with all FinFET and all TFET implementations in near-threshold region.

For hybrid 32-bit CLA, TFETs are used for the top critical path to reduce the longest path delay, and FinFETs are used for the rest of the circuit to reduce switching power and leakage power. The PDP of the hybrid TFET-FinFET CLA circuit is better than the circuits with all FinFET and all TFET implementations in the vicinity of VDD=0.3V. Considering work function variation (WFV) and fin line-edge roughness (LER), the hybrid implementation exhibits comparable PDP variability compared with all FinFET and all TFET implementations at 0.3V.

For hybrid latch circuits (SCCL, LVCL, MTLP and PTL), TFETs are used for critical path to reduce the clock-to-Q delay (Tcq), and FinFETs are used for the rest of the circuits to reduce the power consumption. The hybrid latch circuits are shown to offer comparable or better Tcq while exhibiting superior EDP compared with all TFET implementations. Among the four types of latch circuits, the hybrid LVCL exhibits the most significant Tcq and EDP improvements at low operating voltage (< 0.30V). With WFV and fin LER, the hybrid LVCL exhibits superior and comparable EDP variability compared with all FinFET and all TFET implementations at 0.25V.