標題: Modeling and Characterization of TSV Capacitor and Stable Low-Capacitance Implementation for Wide-I/O Application
作者: Chang, Yao-Yen
Ko, Cheng-Ta
Yu, Tsung-Han
Hsieh, Yu-Sheng
Chen, Kuan-Neng
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: C-V characteristics;modeling;three-dimensional integrated circuit (3DIC);through-silicon via (TSV)
公開日期: 1-Jun-2015
摘要: Equations of the electric field, surface charge, and silicon capacitance with respect to the surface potential of single through-silicon via (TSV) are derived by Poisson\'s equation. Four kinds of charges such as the electrons, holes, and ionized donor/acceptor charges in the p-type silicon substrate are brought into the equations. The numerical results of the surface charge show identical plots to planar MOS capacitor when the TSV radius is larger than 1 mu m. After presenting the fundamental C-V characteristics of one TSV capacitor, a simple design for gaining a stable low TSV capacitance value within a wide operating window (vertical bar V-ow vertical bar = 20 V) is proposed. Cu TSVs in this design are then demonstrated in the scheme of the wafer-level Cu/Sn to BCB hybrid bonding. The design gives the rational power consumption and delay, and the guideline for physical IC design is described in this paper. Without the oxide-trapped charge Q(ot) engineering in TSV oxide liner, neither considerations of the V-FB shifts nor the doping-type selection in silicon substrate, the design facilitates IC engineers to plan the high-speed TSVs at a specific location and to save the cost from TSV engineering simultaneously.
URI: http://dx.doi.org/10.1109/TDMR.2015.2397698
http://hdl.handle.net/11536/127915
ISSN: 1530-4388
DOI: 10.1109/TDMR.2015.2397698
期刊: IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY
Volume: 15
起始頁: 129
結束頁: 135
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