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dc.contributor.authorAltolaguirre, Federico A.en_US
dc.contributor.authorKer, Ming-Douen_US
dc.date.accessioned2015-12-02T02:59:12Z-
dc.date.available2015-12-02T02:59:12Z-
dc.date.issued2015-06-01en_US
dc.identifier.issn1530-4388en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TDMR.2015.2407572en_US
dc.identifier.urihttp://hdl.handle.net/11536/127917-
dc.description.abstractThis paper presents a new RC-based power-rail electrostatic discharge (ESD) clamp circuit, which achieves ultra-low leakage current while maintaining low silicon utilization. A capacitance-boosting technique is used in conjunction with mathematical analysis of area utilization to determine the best set of parameters to achieve the smallest implementation area in silicon. The proposed power-rail ESD clamp circuit has been verified in a 65-nm general-purpose CMOS process, which achieves an ultra-low standby leakage current of 80 nA at 25 degrees C under 1-V bias, as well as ESD robustness of a 4-kV human body model and a 250-V machine model with a silicon area of only 45 mu m x 17 mu m.en_US
dc.language.isoen_USen_US
dc.subjectElectrostatic discharge (ESD)en_US
dc.subjectESD protectionen_US
dc.subjectpower railen_US
dc.subjectleakageen_US
dc.titleArea-Efficient ESD Clamp Circuit With a Capacitance-Boosting Technique to Minimize Standby Leakage Currenten_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TDMR.2015.2407572en_US
dc.identifier.journalIEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITYen_US
dc.citation.volume15en_US
dc.citation.spage156en_US
dc.citation.epage162en_US
dc.contributor.department光電學院zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentCollege of Photonicsen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000356174400005en_US
dc.citation.woscount0en_US
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