完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Shie, Bo-Shiuan | en_US |
dc.contributor.author | Lin, Horng-Chih | en_US |
dc.contributor.author | Huang, Tiao-Yuan | en_US |
dc.date.accessioned | 2015-12-02T02:59:17Z | - |
dc.date.available | 2015-12-02T02:59:17Z | - |
dc.date.issued | 2015-08-01 | en_US |
dc.identifier.issn | 0741-3106 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/LED.2015.2442275 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/128002 | - |
dc.description.abstract | We propose and demonstrate a method which combines film profile engineering (FPE) and a procedure of forming self-aligned bottom gates (SABGs) to fabricate InGaZnO thin-film transistors (TFTs). In the scheme, an ingenious etching procedure was implemented to form the final bottom gate self-aligned to the upper hardmask structure. The fabricated SABG devices show greatly reduced OFF-state leakage as compared with nonself-aligned ones, attributing to the reduction of gate-to-source/drain overlap areas which lowers both parasitic capacitance and gate leakage current. These merits benefit the operation of circuits consisted of TFTs implemented with FPE. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Film profile engineering | en_US |
dc.subject | self-aligned | en_US |
dc.subject | metal oxide | en_US |
dc.subject | InGaZnO | en_US |
dc.subject | thin-film transistor | en_US |
dc.title | Film-Profile Engineered InGaZnO Thin-Film Transistors With Self-Aligned Bottom Gates | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/LED.2015.2442275 | en_US |
dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
dc.citation.volume | 36 | en_US |
dc.citation.spage | 787 | en_US |
dc.citation.epage | 789 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000358570300017 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |