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dc.contributor.authorShie, Bo-Shiuanen_US
dc.contributor.authorLin, Horng-Chihen_US
dc.contributor.authorHuang, Tiao-Yuanen_US
dc.date.accessioned2015-12-02T02:59:17Z-
dc.date.available2015-12-02T02:59:17Z-
dc.date.issued2015-08-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2015.2442275en_US
dc.identifier.urihttp://hdl.handle.net/11536/128002-
dc.description.abstractWe propose and demonstrate a method which combines film profile engineering (FPE) and a procedure of forming self-aligned bottom gates (SABGs) to fabricate InGaZnO thin-film transistors (TFTs). In the scheme, an ingenious etching procedure was implemented to form the final bottom gate self-aligned to the upper hardmask structure. The fabricated SABG devices show greatly reduced OFF-state leakage as compared with nonself-aligned ones, attributing to the reduction of gate-to-source/drain overlap areas which lowers both parasitic capacitance and gate leakage current. These merits benefit the operation of circuits consisted of TFTs implemented with FPE.en_US
dc.language.isoen_USen_US
dc.subjectFilm profile engineeringen_US
dc.subjectself-aligneden_US
dc.subjectmetal oxideen_US
dc.subjectInGaZnOen_US
dc.subjectthin-film transistoren_US
dc.titleFilm-Profile Engineered InGaZnO Thin-Film Transistors With Self-Aligned Bottom Gatesen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2015.2442275en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume36en_US
dc.citation.spage787en_US
dc.citation.epage789en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000358570300017en_US
dc.citation.woscount0en_US
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