Full metadata record
DC FieldValueLanguage
dc.contributor.authorLyu, Rong-Jheen_US
dc.contributor.authorLin, Horng-Chihen_US
dc.contributor.authorHuang, Tiao-Yuanen_US
dc.date.accessioned2015-12-02T02:59:17Z-
dc.date.available2015-12-02T02:59:17Z-
dc.date.issued2015-08-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2015.2445772en_US
dc.identifier.urihttp://hdl.handle.net/11536/128003-
dc.description.abstractRoot cause for the anomalous degradation in the ON-current of film-profile-engineered ZnO thin-film transistors with discrete bottom gates, a new scheme proposed in our previous work, is investigated. Our findings indicate that the deposited source/drain (S/D) metal contact pads are disconnected owing to two TiN wires hung over the S/D regions, which are unintentionally formed during the fabrication of devices. The disconnected S/D metal contacts cause an increase in the S/D series resistance, and thus, the ON-current is degraded. Several ways for addressing this issue are proposed in this letter, including the simple thinning of gate electrode. As the undesirable TiN wires are eliminated, the devices demonstrate enhanced field-effect mobility and uniformity in performance.en_US
dc.language.isoen_USen_US
dc.subjectMetal oxidesen_US
dc.subjectfilm profile engineering (FPE)en_US
dc.subjectZnOen_US
dc.subjectthin-film transistoren_US
dc.titleImpact of Residual Hardmask Wires on the Performance of Film-Profile-Engineered ZnO Thin-Film Transistors With Discrete Bottom Gatesen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2015.2445772en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume36en_US
dc.citation.spage796en_US
dc.citation.epage798en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000358570300020en_US
dc.citation.woscount0en_US
Appears in Collections:Articles