標題: | A Novel Approach Using Discrete Grain-Boundary Traps to Study the Variability of 3-D Vertical-Gate NAND Flash Memory Cells |
作者: | Wang, Pei-Yu Tsui, Bing-Yue 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Flash memory;grain boundaries;polysilicon (poly-Si);variability;vertical gate (VG) |
公開日期: | 1-八月-2015 |
摘要: | The 3-D NAND flash memory architectures will be a future trend, because they provide high memory capacity without aggressively scaling down. A vertical-gate (VG) structure composed of polysilicon (poly-Si) channels is a promising 3-D structure that could facilitate realizing an extremely tight-pitch NAND flash memory cell with high memory capacity. However, the variability of the VG memory cell induced by grain boundaries in the poly-Si channels is a major concern for aggressively scaled-down memory cells. In this paper, a discrete-trap approach is applied to emulate the real trap effects in a 3-D memory cell, and the 3-D structure geometry effects and the variation in the threshold voltage (V-T) induced by the discrete grain-boundary traps are studied. Various Delta V-T behaviors related to the structure geometry and trap position are examined. The effect of varying the body thickness on the Delta V-T is stronger than that of varying the channel width. This paper presents various cases for using the discrete-trap approach to study the variability of V-T in 3-D VG memory cells. |
URI: | http://dx.doi.org/10.1109/TED.2015.2438001 http://hdl.handle.net/11536/128008 |
ISSN: | 0018-9383 |
DOI: | 10.1109/TED.2015.2438001 |
期刊: | IEEE TRANSACTIONS ON ELECTRON DEVICES |
Volume: | 62 |
起始頁: | 2488 |
結束頁: | 2493 |
顯示於類別: | 期刊論文 |