標題: Efficient Algorithm and Fast Hardware Implementation for Multiply-by-(1+2(k))
作者: Wey, Chin-Long
Jui, Ping-Chang
Shiue, Muh-Tian
電機資訊學士班
Undergraduate Honors Program of Electrical Engineering and Computer Science
關鍵字: constant multiplier;ripple carry adder (RCA);carry-lookahead adder (CLA);hybrid adder (HyA);booth algorithm
公開日期: 1-四月-2015
摘要: A constant multiplier performs a multiplication of a data-input with a constant value. Constant multipliers are essential components in various types of arithmetic circuits, such as filters in digital signal processor (DSP) units, and they are prevalent in modern VLSI designs. This study presents an efficient algorithm and fast hardware implementation for performing multiply-by-(1+2(k)) operation with additions. No multiplications are needed. The value of (1+2(k))N can be computed by adding N to its k-bit left-shifted value 2(k)N. The additions can be performed by the full-adder-based (FA-based) ripple carry adder (RCA) for simple architecture. This paper introduces the unit cells for additions (UCAs) to construct the UCA-based RCA which achieves 35% faster than the FA-based RCA in speed performance. Further, in order to improve the speed performance, a simple and modular hybrid adder is presented with the proposed UCA concept, where the carry lookahead adder (CLA) as a module and many of the CLA modules are serially connected in a fashion similar to the RCA. Results show that the hybrid adder significantly improves the speed performance.
URI: http://dx.doi.org/10.1587/transfun.E98.A.966
http://hdl.handle.net/11536/128088
ISSN: 1745-1337
DOI: 10.1587/transfun.E98.A.966
期刊: IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
Volume: E98A
起始頁: 966
結束頁: 974
顯示於類別:期刊論文