完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lai, Bo-Cheng Charles | en_US |
dc.contributor.author | Chen, Kuan-Ting | en_US |
dc.contributor.author | Wu, Ping-Ru | en_US |
dc.date.accessioned | 2015-12-02T02:59:38Z | - |
dc.date.available | 2015-12-02T02:59:38Z | - |
dc.date.issued | 2015-11-01 | en_US |
dc.identifier.issn | 1063-8210 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TVLSI.2014.2370761 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/128385 | - |
dc.description.abstract | The snoopy-based protocol is a widely used cache coherence mechanism for a symmetric multiprocessor (SMP) system. However, this broadcast-based protocol blindly disseminates data sharing information across the system, and introduces many unnecessary data operations. This paper proposes a novel architecture of double-layer counting Bloom filter (DLCBF) to reduce the unnecessary data lookups on the local cache and redundant data transactions on the shared interconnection of an SMP system. By adding an extra filtering layer, the DLCBF effectively exploits the data locality of applications. The two-layer hierarchy reduces the storage size of DLCBF by 18.75%, and achieves 81.99% and 31.36% better filtering rates when compared with a classic Bloom filter (BF) and original counting BF, respectively. When applied on the segmented shared bus of an SMP system, the DLCBF outperforms the previous work by 58% for In-filters and 1.86x for Out-filters. This paper also comprehensively explores the key design parameters of DLCBF, including the sizes of top-layer, bottom-layer, and multilayer design. The results show that enlarging the layer filters enhance the filtering rates of DLCBF, while adding an extra filter layer only provides slight benefit. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Cache memory | en_US |
dc.subject | multicore processing | en_US |
dc.subject | simulation | en_US |
dc.subject | system analysis and design | en_US |
dc.title | A High-Performance Double-Layer Counting Bloom Filter for Multicore Systems | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TVLSI.2014.2370761 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | en_US |
dc.citation.volume | 23 | en_US |
dc.citation.issue | 11 | en_US |
dc.citation.spage | 2473 | en_US |
dc.citation.epage | 2486 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000364209000011 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |