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dc.contributor.authorLai, Bo-Cheng Charlesen_US
dc.contributor.authorChen, Kuan-Tingen_US
dc.contributor.authorWu, Ping-Ruen_US
dc.date.accessioned2015-12-02T02:59:38Z-
dc.date.available2015-12-02T02:59:38Z-
dc.date.issued2015-11-01en_US
dc.identifier.issn1063-8210en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TVLSI.2014.2370761en_US
dc.identifier.urihttp://hdl.handle.net/11536/128385-
dc.description.abstractThe snoopy-based protocol is a widely used cache coherence mechanism for a symmetric multiprocessor (SMP) system. However, this broadcast-based protocol blindly disseminates data sharing information across the system, and introduces many unnecessary data operations. This paper proposes a novel architecture of double-layer counting Bloom filter (DLCBF) to reduce the unnecessary data lookups on the local cache and redundant data transactions on the shared interconnection of an SMP system. By adding an extra filtering layer, the DLCBF effectively exploits the data locality of applications. The two-layer hierarchy reduces the storage size of DLCBF by 18.75%, and achieves 81.99% and 31.36% better filtering rates when compared with a classic Bloom filter (BF) and original counting BF, respectively. When applied on the segmented shared bus of an SMP system, the DLCBF outperforms the previous work by 58% for In-filters and 1.86x for Out-filters. This paper also comprehensively explores the key design parameters of DLCBF, including the sizes of top-layer, bottom-layer, and multilayer design. The results show that enlarging the layer filters enhance the filtering rates of DLCBF, while adding an extra filter layer only provides slight benefit.en_US
dc.language.isoen_USen_US
dc.subjectCache memoryen_US
dc.subjectmulticore processingen_US
dc.subjectsimulationen_US
dc.subjectsystem analysis and designen_US
dc.titleA High-Performance Double-Layer Counting Bloom Filter for Multicore Systemsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TVLSI.2014.2370761en_US
dc.identifier.journalIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMSen_US
dc.citation.volume23en_US
dc.citation.issue11en_US
dc.citation.spage2473en_US
dc.citation.epage2486en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000364209000011en_US
dc.citation.woscount0en_US
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