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dc.contributor.authorLin, Chih-Chienen_US
dc.contributor.authorLiu, Wen-Haoen_US
dc.contributor.authorLi, Yih-Langen_US
dc.date.accessioned2015-12-02T03:00:49Z-
dc.date.available2015-12-02T03:00:49Z-
dc.date.issued2014-01-01en_US
dc.identifier.isbn978-1-4799-2776-0en_US
dc.identifier.issnen_US
dc.identifier.urihttp://hdl.handle.net/11536/128474-
dc.description.abstractAntenna effect is an important issue that critically impacts the reliability and yield of integrated circuits. The dynamic-programming-based (DP-based) layer assignment method has been adopted to minimize antenna violation by enumerating all possible solutions and pruning inferior solutions. However, the complexities of modern circuits have significantly increased, likely causing the DP-based method to consume much more runtime and memory space. In this paper, we propose a skillful method to effectively Diminish Antenna effect in Layer Assignment Stage (DALAS). Unlike previous work that needs to search for separator locations and thus requires exploring much more solution space, DALAS does not need to search for separator locations and can deal with local and global antenna effects while trying to keep total via count and total overflow minimal. Experiment results show that DALAS is the first work to expel all antenna violations with similar via count to that produced by previous works [3][5] for the benchmarks in ISPD\'08 Global Routing Contest.en_US
dc.language.isoen_USen_US
dc.titleSkillfully Diminishing Antenna Effect in Layer Assignment Stageen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2014 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000356616400001en_US
dc.citation.woscount0en_US
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