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dc.contributor.authorYen, Ta-Kangen_US
dc.contributor.authorYu, Bo-Yaoen_US
dc.contributor.authorLai, Bo-Cheng Charlesen_US
dc.date.accessioned2015-12-02T03:00:55Z-
dc.date.available2015-12-02T03:00:55Z-
dc.date.issued2014-01-01en_US
dc.identifier.isbn978-1-4799-4305-0en_US
dc.identifier.issnen_US
dc.identifier.urihttp://dx.doi.org/10.1109/MCSoC.2014.45en_US
dc.identifier.urihttp://hdl.handle.net/11536/128542-
dc.description.abstractGPGPUs have emerged as one of the most widely used throughput processors. Deep multithreading and on-chip cache hierarchy are the two effective designs to achieve high throughput computing in modern GPGPUs. However, excessive multithreading could aggravate the cache contention while conservative multithreading could leave the execution resource under-utilized. Finding a proper design point between the two has become a significant performance factor to GPGPUs. This paper investigates the correlation between caching behavior and multithreading technique. By demonstrating the trade-off issue between the multithreading and cache contention, this paper proposes a multithreading decision scheme to dynamically adjusts the multithreading degree to achieve superior performance. With the proposed decision scheme, the system performance of memory-intensive workloads can be improved by 60% in average.en_US
dc.language.isoen_USen_US
dc.subjectMemory performanceen_US
dc.subjectGPGPUen_US
dc.subjectmultithreadingen_US
dc.subjectdesign and optimizationen_US
dc.titleA Cache Aware Multithreading Decision Scheme on GPGPUsen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/MCSoC.2014.45en_US
dc.identifier.journal2014 IEEE 8TH INTERNATIONAL SYMPOSIUM ON EMBEDDED MULTICORE/MANYCORE SOCS (MCSOC)en_US
dc.citation.spage267en_US
dc.citation.epage272en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000357812800036en_US
dc.citation.woscount0en_US
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