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dc.contributor.authorHu, Kaien_US
dc.contributor.authorDinh, Trung Anhen_US
dc.contributor.authorHo, Tsung-Yien_US
dc.contributor.authorChakrabarty, Krishnenduen_US
dc.date.accessioned2015-12-02T03:00:58Z-
dc.date.available2015-12-02T03:00:58Z-
dc.date.issued2014-01-01en_US
dc.identifier.isbn978-1-4503-3050-3en_US
dc.identifier.issnen_US
dc.identifier.urihttp://dx.doi.org/10.1145/2656106.2656118en_US
dc.identifier.urihttp://hdl.handle.net/11536/128627-
dc.description.abstractRecent advantages in flow-based microfluidic biochips have enabled the emergence of lab-on-a-chip devices for bimolecular recognition and point-of-care disease diagnostics. However, the adoption of flow-based biochips is hampered today by the lack of computer-aided design tools. Manual design procedures not only delay product development but they also inhibit the exploitation of the design complexity that is possible with current fabrication techniques. In this paper, we present the first practical problem formulation for automated control-layer design in flow-based microfluidic VLSI (mVLSI) biochips and propose a systematic approach for solving this problem. Our goal is to find an efficient routing solution for control-layer design with a minimum number of control pins. The pressure-propagation delay, an intrinsic physical phenomenon in mVLSI biochips, is minimized in order to reduce the response time for valves, decrease the pattern set-up time, and synchronize valve actuation. Two fabricated flow-based devices and five synthetic benchmarks are used to evaluate the proposed optimization method. Compared with manual control-layer design and a baseline approach, the proposed approach leads to fewer control pins, better timing behavior, and shorter channel length in the control layer.en_US
dc.language.isoen_USen_US
dc.titleControl-Layer Optimization for Flow-Based mVLSI Microfluidic Biochipsen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1145/2656106.2656118en_US
dc.identifier.journal2014 INTERNATIONAL CONFERENCE ON COMPILERS, ARCHITECTURE AND SYNTHESIS FOR EMBEDDED SYSTEMS (CASES)en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000360811500016en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper