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dc.contributor.authorWang, Pei-Yuen_US
dc.contributor.authorTsui, Bing-Yueen_US
dc.date.accessioned2016-03-28T00:04:08Z-
dc.date.available2016-03-28T00:04:08Z-
dc.date.issued2015-12-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2015.2487563en_US
dc.identifier.urihttp://hdl.handle.net/11536/129349-
dc.description.abstractA CMOS process compatible p-channel tunnel field-effect transistor (TFET) with an epitaxial tunnel layer (ETL) structure is demonstrated experimentally. The fabricated ETL p-TFET exhibits high tunneling current (I-ON similar to 0.17 mu A/mu m at vertical bar V-G vertical bar = 0.5 V after V-TH adjustment), ultra-low OFF-state current, and good average subthreshold swing (S.S. similar to 100 mV/decade up to 10 nA/mu m). Overall performance exceeds that of the current state-of-the-art Ge-based planar p-TFETs.en_US
dc.language.isoen_USen_US
dc.subjectTunnel field-effect transistoren_US
dc.subjectband to band tunnelingen_US
dc.subjectsubthreshold swing (SS)en_US
dc.titleExperimental Demonstration of p-Channel Germanium Epitaxial Tunnel Layer (ETL) Tunnel FET With High Tunneling Current and High ON/OFF Ratioen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2015.2487563en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume36en_US
dc.citation.issue12en_US
dc.citation.spage1264en_US
dc.citation.epage1266en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000365295300003en_US
dc.citation.woscount0en_US
Appears in Collections:Articles