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dc.contributor.authorLiu, Chia-Hungen_US
dc.contributor.authorShen, Kuo-Chengen_US
dc.contributor.authorHuang, Juinn-Daren_US
dc.date.accessioned2016-03-28T00:04:08Z-
dc.date.available2016-03-28T00:04:08Z-
dc.date.issued2015-12-01en_US
dc.identifier.issn0278-0070en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCAD.2015.2440312en_US
dc.identifier.urihttp://hdl.handle.net/11536/129352-
dc.description.abstractSample preparation is one of the essential processes for most on-chip biochemical applications. During this process, raw reactants are diluted to specific concentration values. Current sample preparation algorithms are generally created for digital microfluidic biochips with the (1:1) mixing model. For other biochip architectures supporting multiple mixing models, such as flow-based microfluidic biochips, there is still no dedicated solution yet. Hence, in this paper, we propose the first sample preparation method dedicated to microfluidic biochips with various mixing models, named tree pruning and grafting (TPG) algorithm. It starts with a dilution tree created by regarding the (1: 1) mixing model only, and then applies TPG through a bottom-up dynamic programming strategy to obtain a solution with minimal reactant consumption. Experimental results show that our algorithm can save reactant amount by up to 69% against the well-known bit-scanning method on a biochip with a four-segment mixer. Even compared with the state-of-the-art reactant minimization algorithm, it still achieves a reactant reduction of 37%. Therefore, it is convincing that the TPG algorithm is a promising sample preparation solution for biochip architectures that support various mixing models.en_US
dc.language.isoen_USen_US
dc.subjectBiochipen_US
dc.subjectdilutionen_US
dc.subjectflow-based microfluidic biochip (FMFB)en_US
dc.subjectmixing modelen_US
dc.subjectreactant minimizationen_US
dc.subjectsample preparationen_US
dc.titleReactant Minimization for Sample Preparation on Microfluidic Biochips With Various Mixing Modelsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCAD.2015.2440312en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMSen_US
dc.citation.volume34en_US
dc.citation.issue12en_US
dc.citation.spage1918en_US
dc.citation.epage1927en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000365222400003en_US
dc.citation.woscount0en_US
Appears in Collections:Articles