標題: A 5.8 mW Continuous-Time Delta Sigma Modulator With 20 MHz Bandwidth Using Time-Domain Flash Quantizer
作者: Chen, Zong-Yi
Hung, Chung-Chih
電機資訊學士班
Undergraduate Honors Program of Electrical Engineering and Computer Science
關鍵字: Analog-to-digital converter;continuous-time;data weighted averaging;delta-sigma modulator;low power;time-domain flash quantizer;voltage-to-time converter
公開日期: 1-Dec-2015
摘要: This paper presents a power-efficient realization of a third-order continuous-time delta-sigma (CT - Delta Sigma) modulator with 3-bit time-domain flash quantizer (TDFQ) and data-weighted averaging (DWA) based on the shifter output and input. Using the time-domain quantizer can overcome design issues in low voltage supply during CMOS downscaling. The CT - Delta Sigma modulator uses the TDFQ instead of a voltage-domain quantizer to reduce power consumption. The proposed TDFQ solves the linearity problem of the delay-based voltage-to-time converter (VTC) without calibration circuit while also increasing the quantizer input range and saving energy. Moreover, in order to reduce the mismatch effects of a multibit DAC and achieve low power consumption, implementation of a low-power DWA circuit is proposed without using a digital adder to calculate pointer for controlling barrel shift circuit. This chip was fabricated in CMOS 90 nm process. The proposed CT - Delta Sigma modulator consumes 5.8 mW from 1.0 V and achieves peak SNDR of 65.3 dB over the 20 MHz bandwidth, which results in FOM_W = 96.3 fJ/level and FOM_S = 161 dB.
URI: http://dx.doi.org/10.1109/JETCAS.2015.2502167
http://hdl.handle.net/11536/129548
ISSN: 2156-3357
DOI: 10.1109/JETCAS.2015.2502167
期刊: IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS
起始頁: 574
結束頁: 583
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