完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Bin, Shu-Yung | en_US |
dc.contributor.author | Lin, Shih-Feng | en_US |
dc.contributor.author | Cheng, Ya-Ching | en_US |
dc.contributor.author | Liau, Wen-Rong | en_US |
dc.contributor.author | Hou, Alex | en_US |
dc.contributor.author | Chao, Mango C. -T. | en_US |
dc.date.accessioned | 2016-03-28T00:04:24Z | - |
dc.date.available | 2016-03-28T00:04:24Z | - |
dc.date.issued | 2016-02-01 | en_US |
dc.identifier.issn | 1063-8210 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TVLSI.2015.2418998 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/129641 | - |
dc.description.abstract | An SRAM-array test structure provides the capability of directly measuring the characteristics of each transistor and the read/write metrics for each static random access memory (SRAM) cell in the array. However, the total test time of measuring the read/write metrics takes longer than that of measuring each transistor\'s characteristics. This paper presents a model-fitting framework to predict the average read/write metrics of the SRAM cells in a lithography shot using only the measured transistor characteristics. The proposed framework is validated through the measurement result of 4750 samples of a 128-bit SRAM-array test structure implemented in a United Microelectronics Corporation 28-nm process technology. The experimental results show that the learned models can achieve at least 97.77% R-square on fitting the shot-level read static noise margin, write margin, and read current based on 2375-sample testing data. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Array test-structure | en_US |
dc.subject | model-fitting | en_US |
dc.subject | process monitor | en_US |
dc.subject | SRAM characterization | en_US |
dc.subject | test-time reduction | en_US |
dc.title | Predicting Shot-Level SRAM Read/Write Margin Based on Measured Transistor Characteristics | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TVLSI.2015.2418998 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | en_US |
dc.citation.volume | 24 | en_US |
dc.citation.spage | 625 | en_US |
dc.citation.epage | 637 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000369479500019 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |