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dc.contributor.authorChang, C. -W.en_US
dc.contributor.authorChang, K. -Y.en_US
dc.contributor.authorChu, Y. -H.en_US
dc.contributor.authorJou, S. -J.en_US
dc.date.accessioned2016-03-28T00:04:25Z-
dc.date.available2016-03-28T00:04:25Z-
dc.date.issued2016-01-21en_US
dc.identifier.issn0013-5194en_US
dc.identifier.urihttp://dx.doi.org/10.1049/el.2015.1779en_US
dc.identifier.urihttp://hdl.handle.net/11536/129660-
dc.description.abstractA near-threshold all-digital phase-locked loop (ADPLL) with a power management unit (PMU) is presented to make the proposed ADPLL work reliably across variations and power consumption as well is reduced. When operated under near-threshold condition from 0.52 to 0.58 V V-DD, the gated digitally controlled oscillator frequency range is from 90.8 to 245.7 MHz. When the ADPLL is operated at 0.52 V V-DD, a lock-in time of 9.5 mu s at 100 MHz output clock frequency is measured with an rms period jitter of 0.17% UI. With the PMU, the ADPLL power reduction at 130 MHz output frequency is 39% and the buck converter power consumption is nearly 30 mu W. Consequently, the proposed ADPLL with PMU is suitable to event-driven or low-voltage applications.en_US
dc.language.isoen_USen_US
dc.titleNear-threshold all-digital PLL with dynamic voltage scaling power managementen_US
dc.typeArticleen_US
dc.identifier.doi10.1049/el.2015.1779en_US
dc.identifier.journalELECTRONICS LETTERSen_US
dc.citation.volume52en_US
dc.citation.spage109en_US
dc.citation.epage112en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000368537800009en_US
dc.citation.woscount0en_US
Appears in Collections:Articles