標題: Near-threshold all-digital PLL with dynamic voltage scaling power management
作者: Chang, C. -W.
Chang, K. -Y.
Chu, Y. -H.
Jou, S. -J.
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 21-Jan-2016
摘要: A near-threshold all-digital phase-locked loop (ADPLL) with a power management unit (PMU) is presented to make the proposed ADPLL work reliably across variations and power consumption as well is reduced. When operated under near-threshold condition from 0.52 to 0.58 V V-DD, the gated digitally controlled oscillator frequency range is from 90.8 to 245.7 MHz. When the ADPLL is operated at 0.52 V V-DD, a lock-in time of 9.5 mu s at 100 MHz output clock frequency is measured with an rms period jitter of 0.17% UI. With the PMU, the ADPLL power reduction at 130 MHz output frequency is 39% and the buck converter power consumption is nearly 30 mu W. Consequently, the proposed ADPLL with PMU is suitable to event-driven or low-voltage applications.
URI: http://dx.doi.org/10.1049/el.2015.1779
http://hdl.handle.net/11536/129660
ISSN: 0013-5194
DOI: 10.1049/el.2015.1779
期刊: ELECTRONICS LETTERS
Volume: 52
起始頁: 109
結束頁: 112
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