完整後設資料紀錄
DC 欄位語言
dc.contributor.authorHuang, Wen-Tsungen_US
dc.contributor.authorLi, Yimingen_US
dc.date.accessioned2016-03-28T00:05:42Z-
dc.date.available2016-03-28T00:05:42Z-
dc.date.issued2014-01-01en_US
dc.identifier.isbn978-1-4799-5288-5en_US
dc.identifier.issn1946-1569en_US
dc.identifier.urihttp://hdl.handle.net/11536/129769-
dc.description.abstractIn this work, the DC characteristic variability of 14-nm-gate HKMG trapezoidal bulk FinFET induced by different line edge roughness (LER) is for the first time studied by using experimentally validated 3D device simulation. By considering a time-domain Gaussian noise function, we compare four types of LER: Fin-LER inclusive of resist-LER and spacer-LER, sidewall-LER, and gate-LER for the trapezoidal bulk FinFET with respect to different fin angles. The resist-LER and sidewall-LER have large impact on characteristics fluctuation. For each type of LER, the Vth fluctuation is comparable among fin angles.en_US
dc.language.isoen_USen_US
dc.subjectline edge roughnessen_US
dc.subjectfin-LERen_US
dc.subjectsidewall-LERen_US
dc.subjectgate-LERen_US
dc.subjecttrapezoidal bulk FinFETen_US
dc.titleThe Impact of Fin/Sidewall/Gate Line Edge Roughness on Trapezoidal Bulk FinFET Devicesen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2014 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD)en_US
dc.citation.spage281en_US
dc.citation.epage284en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department傳播研究所zh_TW
dc.contributor.department電機資訊學士班zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentInstitute of Communication Studiesen_US
dc.contributor.departmentUndergraduate Honors Program of Electrical Engineering and Computer Scienceen_US
dc.identifier.wosnumberWOS:000364919800071en_US
dc.citation.woscount0en_US
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