完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Huang, Chia-Chi | en_US |
dc.contributor.author | Lin, Chang-Tzu | en_US |
dc.contributor.author | Liao, Wei-Syun | en_US |
dc.contributor.author | Lee, Chieh-Jui | en_US |
dc.contributor.author | Chen, Hung-Ming | en_US |
dc.contributor.author | Lee, Chia-Hsin | en_US |
dc.contributor.author | Kwai, Ding-Ming | en_US |
dc.date.accessioned | 2016-03-28T00:05:45Z | - |
dc.date.available | 2016-03-28T00:05:45Z | - |
dc.date.issued | 2014-01-01 | en_US |
dc.identifier.isbn | 978-1-4799-6492-5 | en_US |
dc.identifier.issn | 1063-6404 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/129834 | - |
dc.description.abstract | There are many works on the power network design and prototyping for digital designs, however some usual and practical design concerns are not addressed. In this work, we present a realistic power network design methodology without IR violation certified by state-of-the-art commercial tool. Our work integrates analysis, optimization and synthesis of power network. In particular, we consider thermal effect and power pad\'s positions during the prototyping of power network. A scenario in placement regarding the violation of design rules is considered and resolved by maximum flow algorithm at the same stage. After the synthesis of initial power network, we generate a sensitivity matrix which is correlated with nodal voltage and resistances of net and via in metal layers. Furthermore, a Sequential Linear Programming(SLP) will be applied to adjust the sensitivity matrix iteratively until the IR drop constraint is satisfied. Our work is experimented on a real design in TSMC 65nm LP process, and the result validates our framework that the IR-Drop can be reduced to 2% of supply voltage. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Improving Power Delivery Network Design by Practical Methodologies | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2014 32ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD) | en_US |
dc.citation.spage | 230 | en_US |
dc.citation.epage | 235 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000369867800034 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |