完整後設資料紀錄
DC 欄位語言
dc.contributor.author林鴻志zh_TW
dc.contributor.authorLIN HORNG-CHIHen_US
dc.date.accessioned2016-03-28T08:17:36Z-
dc.date.available2016-03-28T08:17:36Z-
dc.date.issued2015en_US
dc.identifier.govdocNSC102-2221-E009-097-MY3zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/130230-
dc.identifier.urihttps://www.grb.gov.tw/search/planDetail?id=11278287&docId=457116en_US
dc.description.abstract在本專題計畫中,主要針對新興的積體電路後段主動元件技術,我們提出了數種自行構思的金屬氧化物元件結構與其製程,包括創新的自我組成薄膜電晶體、平面結構互補式電阻切換元件、垂直通道電晶體、以及奈米線電晶體。自我組成電晶體的作法不同於以往使用鎳製遮罩的製程,而是採用黃光微影的方式製作,能輕易達到深次微米尺度、高均勻性以及高製程靈活度的目的,有利於電路上的應用。同時,藉此創新製程也能夠達到平面結構互補式電阻切換元件之製作,大幅改善了以往垂直結構元件的製程複雜性以及變異性。此外,我們亦提出了可自我對準的1T2R元件結構與製程,以簡單的製程同時完成薄膜電晶體以及電阻式記憶體的整合,實現多功能操作。垂直通道電晶體製作的目的,在於以結構設計的方式使得電晶體具有短通道以及相當大的寬高比,藉此提升元件特性。而為了探討元件微縮後遭遇的現象,本計畫中亦以自行開發的製程製作通道長度< 100奈米的奈米線電晶體,分析其電特性以及深入探討奈米等級元件所面臨的雜訊與隨機電報擾動等特性。本計畫中開發的元件對於電晶體特性的提升、製程的簡化、尺寸的微縮以及物理機制的釐清都具有巨大的潛力,相信能在積體電路後段主動元件的研究上有重大的突破。zh_TW
dc.description.abstractIn this project, with the main focus put on the newly emerged active BEOL device scope, we propose several novel metal-oxide device schemes and their fabrication methods, including revolutionary self-assembled thin film transistor (SATFT), planar complementary resistive switching (P-CRS), vertical channel TFT, and nanowire (NW) transistor. In the innovative process of SATFT, patterning of the device structure is carried out photolithography instead of using a shadow mask, hence deep sub-micron SATFT can be promptly attained with good uniformity and more process flexibility. These properties are essential for construction of practical circuits. Furthermore, with slight modifications, the aforementioned process can be further applied to fabricate P-CRS and 1T2R devices. The high complexity and variability of conventional vertical CRS can be greatly relieved. Vertical channel structures are developed as well and are expected to achieve high performance owing to its capability in shortening the channel and increasing the channel width/length ratio. To investigate the phenomena occurring in nano-scaled devices, a novel process is also developed to fabricate NW transistors with sub-100nm channel lengths. Basic electrical characteristics and noise performance of the fabricated devices will be characterized and explored. The device technologies developed in this project are expected to offer great potential for realization of embedded BEOL devices and circuits. We strongly believe that the results of this project will draw impacts on the development of metal-oxide devices.en_US
dc.description.sponsorship科技部zh_TW
dc.language.isozh_TWen_US
dc.subject自我組成薄膜電晶體zh_TW
dc.subject平面結構互補式電阻切換元件zh_TW
dc.subject垂直通道電晶體zh_TW
dc.subject1T2R元件zh_TW
dc.subject奈米線電晶體zh_TW
dc.subject隨機電報擾動zh_TW
dc.subjectself-assembled thin film transistoren_US
dc.subjectplanar complementary resistive switchingen_US
dc.subject1T2Ren_US
dc.subjectvertical channel TFTen_US
dc.subjectnanowire transistoren_US
dc.subjectrandom telegraph noiseen_US
dc.title金屬氧化物後段主動元件技術開發zh_TW
dc.titleDevelopment of Active Beol Metal-Oxide Device Technologiesen_US
dc.typePlanen_US
dc.contributor.department國立交通大學電子工程學系及電子研究所zh_TW
顯示於類別:研究計畫