整合反鐵電操作及低臨界漏電流之低功耗負電容鐵電電晶體技術研發

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	張俊彥	zh_TW
dc.contributor.author	鄭淳護	zh_TW
dc.date.accessioned	2016-12-20T03:56:43Z	-
dc.date.available	2016-12-20T03:56:43Z	-
dc.date.issued	2016	en_US
dc.identifier.govdoc	MOST105-2221-E009-139-MY3	zh_TW
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=11876421&docId=484551	en_US
dc.identifier.uri	http://hdl.handle.net/11536/131790	-
dc.description.abstract		zh_TW
dc.description.abstract		en_US
dc.description.sponsorship	科技部	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject		zh_TW
dc.subject		en_US
dc.title	整合反鐵電操作及低臨界漏電流之低功耗負電容鐵電電晶體技術研發	zh_TW
dc.title	Development of Low-Power Ferroelectric Negative-Capacitance Transistor Integrated with Antiferroelectric Operation and Low Subthreshold Leakage	en_US
dc.type	Plan	en_US
dc.contributor.department	國立交通大學電子工程學系及電子研究所	zh_TW
顯示於類別：	研究計畫