具高微縮性及陡峭次臨界擺幅之全包覆式閘極無接面電晶體研究開發

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	張俊彥	zh_TW
dc.contributor.author	鄭淳護	zh_TW
dc.date.accessioned	2016-12-20T03:56:45Z	-
dc.date.available	2016-12-20T03:56:45Z	-
dc.date.issued	2016	en_US
dc.identifier.govdoc	MOST105-2221-E009-140-MY3	zh_TW
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=11882040&docId=486133	en_US
dc.identifier.uri	http://hdl.handle.net/11536/131816	-
dc.description.abstract		zh_TW
dc.description.abstract		en_US
dc.description.sponsorship	科技部	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject		zh_TW
dc.subject		en_US
dc.title	具高微縮性及陡峭次臨界擺幅之全包覆式閘極無接面電晶體研究開發	zh_TW
dc.title	Investigation of Gate-All-Around Junctionless Transistor Featuring High Scalability and Steep Subthreshold Swing	en_US
dc.type	Plan	en_US
dc.contributor.department	國立交通大學電子工程學系及電子研究所	zh_TW
顯示於類別：	研究計畫