利用用戶可程式化閘陣列之資料流合成

Full metadata record

DC Field	Value	Language
dc.contributor.author	項春申	zh_TW
dc.date.accessioned	2016-12-20T03:57:07Z	-
dc.date.available	2016-12-20T03:57:07Z	-
dc.date.issued	1993	en_US
dc.identifier.govdoc	NSC82-0404-E009-401	zh_TW
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=46066&docId=6611	en_US
dc.identifier.uri	http://hdl.handle.net/11536/132170	-
dc.description.abstract		zh_TW
dc.description.abstract		en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject		zh_TW
dc.subject		en_US
dc.title	利用用戶可程式化閘陣列之資料流合成	zh_TW
dc.title	Datapath Synthesis Using FPGA	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學電子研究所	zh_TW
Appears in Collections:	Research Plans