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dc.contributor.author侯拓宏en_US
dc.date.accessioned2016-12-20T05:04:22Z-
dc.date.available2016-12-20T05:04:22Z-
dc.date.issued2016-07-01en_US
dc.identifier.govdocH01L021/8247zh_TW
dc.identifier.govdocH01L027/115zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/132287-
dc.description.abstract一種三維反或型快閃記憶體包含多個導電層、多個介電層、多個通道層、多個穿隧隔離層、多個電荷捕捉層、多個電荷阻擋層以及多個閘極電極。多個導電層以及多個介電層交錯配置,以使多個導電層彼此電性隔離。通道層、穿隧隔離層、電荷捕捉層、電荷阻擋層以及閘極電極依序設置於多個導電層以及多個介電層之一側表面,其中,二個相鄰導電層分別作為一電晶體之一源極以及一汲極,並與對應之閘極電極定義一記憶體單元。依據此結構,多個記憶體單元能夠以三維架構配置以提升單位晶片面積之位元密度,且每一記憶體單元能夠定址且存取。zh_TW
dc.language.isozh_TWen_US
dc.title三維反或型快閃記憶體及其製造方法zh_TW
dc.typePatentsen_US
dc.citation.patentcountryTWNzh_TW
dc.citation.patentnumber201624624zh_TW
Appears in Collections:Patents


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