完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Shen, Wen-Wei | en_US |
dc.contributor.author | Chen, Kuan-Neng | en_US |
dc.date.accessioned | 2019-04-03T06:37:05Z | - |
dc.date.available | 2019-04-03T06:37:05Z | - |
dc.date.issued | 2017-01-19 | en_US |
dc.identifier.issn | 1556-276X | en_US |
dc.identifier.uri | http://dx.doi.org/10.1186/s11671-017-1831-4 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/133029 | - |
dc.description.abstract | 3D integration with through-silicon via (TSV) is a promising candidate to perform system-level integration with smaller package size, higher interconnection density, and better performance. TSV fabrication is the key technology to permit communications between various strata of the 3D integration system. TSV fabrication steps, such as etching, isolation, metallization processes, and related failure modes, as well as other characterizations are discussed in this invited review paper. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Through-silicon via (TSV) | en_US |
dc.subject | Three-dimensional integrated circuit (3D IC) | en_US |
dc.title | Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV) | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1186/s11671-017-1831-4 | en_US |
dc.identifier.journal | NANOSCALE RESEARCH LETTERS | en_US |
dc.citation.volume | 12 | en_US |
dc.citation.spage | 0 | en_US |
dc.citation.epage | 0 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000392520900005 | en_US |
dc.citation.woscount | 16 | en_US |
顯示於類別: | 期刊論文 |