完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.author | Lyu, Rong-Jhe | en_US |
| dc.contributor.author | Shie, Bo-Shiuan | en_US |
| dc.contributor.author | Lin, Horng-Chih | en_US |
| dc.contributor.author | Li, Pei-Wen | en_US |
| dc.contributor.author | Huang, Tiao-Yuan | en_US |
| dc.date.accessioned | 2017-04-21T06:56:32Z | - |
| dc.date.available | 2017-04-21T06:56:32Z | - |
| dc.date.issued | 2017-03 | en_US |
| dc.identifier.issn | 0018-9383 | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/TED.2016.2646221 | en_US |
| dc.identifier.uri | http://hdl.handle.net/11536/133146 | - |
| dc.description.abstract | We report an exquisite, film- profileengineering approach for producing nanometer-scale channel-length (L) ZnO thin-film transistors (TFTs). The scheme is based on a unique laminated structure in conjunction with a well-designed etching process for building a slender, suspending bridge that shadows the subsequent deposition of pivotal thin films of ZnO and gate oxide as well as simultaneously defines L of the TFTs. With the approach, we have ingeniously downscaled L of ZnO TFTs to as short as 10 nm. The experimental ZnO TFTs of L = 50 and 30 nm, respectively, exhibit excellent performance in terms of high on/off current ratio of 7.9x10(7) and 4.2x10(7), superior subthreshold swing of 92 and 95 mV/decade, and small drain induced barrier lowering of 0.1 and 0.29 V/V. Remarkably the nanometerscale ZnO TFTs possess excellent device uniformity. Furthermore, the precise control over the geometrical sizes for the channel length enables the fabrication of ultrashort ZnO TFTs of L as short as 10 nm with reasonable gate transfer characteristics. | en_US |
| dc.language.iso | en_US | en_US |
| dc.subject | Film profile engineering (FPE) | en_US |
| dc.subject | metal oxide (MO) | en_US |
| dc.subject | short channel effects (SCEs) | en_US |
| dc.subject | thin-film transistors | en_US |
| dc.subject | (TFTs) | en_US |
| dc.subject | ZnO | en_US |
| dc.title | Downscaling Metal-Oxide Thin-Film Transistors to Sub-50 nm in an Exquisite Film-Profile Engineering Approach | en_US |
| dc.identifier.doi | 10.1109/TED.2016.2646221 | en_US |
| dc.identifier.journal | IEEE TRANSACTIONS ON ELECTRON DEVICES | en_US |
| dc.citation.volume | 64 | en_US |
| dc.citation.issue | 3 | en_US |
| dc.citation.spage | 1069 | en_US |
| dc.citation.epage | 1075 | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.identifier.wosnumber | WOS:000396056700049 | en_US |
| 顯示於類別: | 期刊論文 | |

